Patents by Inventor Kouji Mizowaki

Kouji Mizowaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer manufacturing method
    Patent number: 8545712
    Abstract: In a method of manufacturing semiconductor wafers, front and back surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 ?m to 5 ?m; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 ?m or less in total.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: October 1, 2013
    Assignee: Sumco Techxiv Corporation
    Inventors: Hiroshi Takai, Kenji Satomura, Yuichi Nakayoshi, Katsutoshi Yamamoto, Kouji Mizowaki
  • SEMICONDUCTOR WAFER MANUFACTURING METHOD
    Publication number: 20100285665
    Abstract: In a method of manufacturing semiconductor wafers, front and hack surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 ?m to 5 ?m; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 ?m or less in total.
    Type: Application
    Filed: September 11, 2008
    Publication date: November 11, 2010
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Hiroshi Takai, Kenji Satomura, Yuichi Nakayoshi, Katsutoshi Yamamoto, Kouji Mizowaki