Abstract: A semiconductor device includes first and second wiring layers, and first and second via plugs. The first wiring layer has parallel tracks along which wirings are laid out, the tracks including first and second outer tracks and an inner track between the first and second outer tracks, the wirings including a first line laid out along the first outer track and having an end portion that is laid out along the first outer track, and a second line laid out along the inner track and having an end portion that is laid out along the first outer track. The first via plug is in contact with the end portion of the first line and extends between the first and second wiring layers, and the second via plug is in contact with the end portion of the second line and extends between the first and second wiring layers.

Abstract: A semiconductor device includes an active region, and an edge seal formed on at least a portion of an outer edge of the active region. The edge seal includes a first stacked body having a first conductive layer, and a second stacked body having a second conductive layer. The first conductive layer is coupled to a first voltage, the second conductive layer is coupled to a second voltage different from the first voltage, and the first conductive layer faces the second conductive layer.

Abstract: A semiconductor storage device of an embodiment includes a wiring layer M1 and a wiring layer M2. The wiring layer M1 includes a signal line through which a data signal is transferred, and a plurality of dummy patterns formed of a material same as a material of the signal line. The wiring layer M2 includes a voltage supply line through which voltage Vdd is supplied and another voltage supply line through which voltage Vss is supplied. Each of the dummy patterns is electrically connected with any one of the voltage supply lines. In a dummy pattern disposed adjacent to the signal line, a surface facing the signal line is constituted by a first surface positioned at a first distance to the signal line and a second surface positioned at a second distance to the signal line, the second distance being different from the first distance.

Abstract: A semiconductor device includes first and second wiring layers, and first and second via plugs. The first wiring layer has parallel tracks along which wirings are laid out, the tracks including first and second outer tracks and an inner track between the first and second outer tracks, the wirings including a first line laid out along the first outer track and having an end portion that is laid out along the first outer track, and a second line laid out along the inner track and having an end portion that is laid out along the first outer track. The first via plug is in contact with the end portion of the first line and extends between the first and second wiring layers, and the second via plug is in contact with the end portion of the second line and extends between the first and second wiring layers.

Abstract: According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

Abstract: A semiconductor storage device of an embodiment includes a wiring layer M1 and a wiring layer M2. The wiring layer M1 includes a signal line through which a data signal is transferred, and a plurality of dummy patterns formed of a material same as a material of the signal line. The wiring layer M2 includes a voltage supply line through which voltage Vdd is supplied and another voltage supply line through which voltage Vss is supplied. Each of the dummy patterns is electrically connected with any one of the voltage supply lines. In a dummy pattern disposed adjacent to the signal line, a surface facing the signal line is constituted by a first surface positioned at a first distance to the signal line and a second surface positioned at a second distance to the signal line, the second distance being different from the first distance.

Abstract: A semiconductor device includes first and second wiring layers, and first and second via plugs. The first wiring layer has parallel tracks along which wirings are laid out, the tracks including first and second outer tracks and an inner track between the first and second outer tracks, the wirings including a first line laid out along the first outer track and having an end portion that is laid out along the first outer track, and a second line laid out along the inner track and having an end portion that is laid out along the first outer track. The first via plug is in contact with the end portion of the first line and extends between the first and second wiring layers, and the second via plug is in contact with the end portion of the second line and extends between the first and second wiring layers.

Abstract: According to one embodiment, a layout verification apparatus includes a design section, a layout creation section, a first verification section and a second verification section. One of the first and second verification sections includes a filter processing section which executes a filter processing of a verification target element to be verified by a mask data used to a manufacture of the semiconductor integrated circuit, and the verification target element to be verified needs an ion implantation. The filter processing section comprises a first logic section which executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified.

Abstract: Data of traffic with long-range dependence characteristics is generated by a host terminal and transferred to a memory arranged on a board. The memory stores the traffic data comprising at least one of the number of IP packets output per unit time and total number of bytes, a set value of each parameter of the generated IP packets (i.e., packet length table) and an IP address table. A packet generation section refers to the data in the memory to generate traffic with long-range dependence characteristics at a speed corresponding to a high-speed network. As a result, the behavior of the network at the time of application of the load can be measured before the actual use of the network. According to the present invention, a traffic generation apparatus that can supply the actual network with a load close to the real traffic can be provided.

Abstract: A seat cushion comprises a cushion body portion including a storage recess and a cushion bottom portion covering the storage recess so as to selectively open or close it. A supplementary seat comprises a supplementary seat back which is pivotally supported so as to rotate in the longitudinal direction and a supplementary seat cushion formed separately from the supplementary seat back. The supplementary seat cushion is configured so as to selectively take a sitting position, where it is located at the side of the seat cushion, and a stored position, where it is stored in the storage recess. Accordingly, since only the supplementary seat cushion is stored in the storage recess, the deterioration of comfortable ride caused by the high-sitting point can be suppressed. Also, the supplementary seat back can be used as a armrest or the like.

Abstract: A seat cushion comprises a cushion body portion including a storage recess and a cushion bottom portion covering the storage recess so as to selectively open or close it. A supplementary seat comprises a supplementary seat back which is pivotally supported so as to rotate in the longitudinal direction and a supplementary seat cushion formed separately from the supplementary seat back. The supplementary seat cushion is configured so as to selectively take a sitting position, where it is located at the side of the seat cushion, and a stored position, where it is stored in the storage recess.

Abstract: A packet repeater (e.g., gateway) is applicable to an integrated digital network system which incorporates a first network (e.g., Internet) and a second network (e.g., satellite communication system) comprising an upstream line and a downstream line which are asymmetrical with respect to each other in data transmission speed. In the packet repeater, specific data (e.g., TCP data) are extracted from plural packets and are assembled together into a single transmission packet on the basis of the maximal amount of storable data, which is greater than the maximal segment size notified from a receiver under conditions in which the reception window size fulfills the maximal amount of storable data.

Abstract: A traffic monitoring system enabling a manager to manage a plurality of traffic monitors in a centralized manner with a desired specification and to effectively utilize a traffic analysis result of each traffic monitor for network management is provided. The manager 1 loads a management application program to the manager itself and executes the program (S1). The manager 1 transfers the management application program to each active monitor 2 to allow the management application program to be executed (S2 and S3). Each active monitor 2 provides an analysis result to the manager 1 in response to a request (S4) from the manager 1 (S5). Each active monitor 2 stops a packet analysis program in response to a request (S6) from the manager 1 and unloads the packet analysis program. After collecting the analysis result, the manager 1 stops and unloads the management application program (S8).

Abstract: When an access from an intruder is detected, a destination rewriting section 441 of a converting section 44 rewrites a destination [regular] which has been registered in an access command [http . . . /regular/doc] to a directory [decoy] of a decoy region 42. A communication application 43 accesses the decoy region 42 designated by the access command. A response converting section 442 of the converting section 44 rewrites a response [success/decoy/doc] returned from the communication application 43 to the content [success/regular/doc] expressing a message where the access to the regular region 41 has been succeeded.

Abstract: Data of traffic with long-range dependence characteristics is generated by a host terminal and transferred to a memory arranged on a board. The memory stores the traffic data comprising at least one of the number of IP packets output per unit time and total number of bytes, a set value of each parameter of the generated IP packets (i.e., packet length table) and an IP address table. A packet generation section refers to the data in the memory to generate traffic with long-range dependence characteristics at a speed corresponding to a high-speed network. As a result, the behavior of the network at the time of application of the load can be measured before the actual use of the network. According to the present invention, a traffic generation apparatus that can supply the actual network with a load close to the real traffic can be provided.

Abstract: A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

Abstract: A semiconductor memory device comprises a page access mode, a plurality of sense amplifiers for detecting data read from a plurality of memory cells selected based on first address inputs A2 to An, a plurality of latch circuits for latching data from the plurality of sense amplifiers, a reading circuit for reading latch data based on second address inputs A0 and A1 corresponding to the plurality of latch circuits, and a control circuit for controlling the sense amplifier to be activated when only the first address input or both first and second address inputs are changed, and to be inactivated when only the second address input is changed.