Abstract: A semiconductor device includes first and second wiring layers, and first and second via plugs. The first wiring layer has parallel tracks along which wirings are laid out, the tracks including first and second outer tracks and an inner track between the first and second outer tracks, the wirings including a first line laid out along the first outer track and having an end portion that is laid out along the first outer track, and a second line laid out along the inner track and having an end portion that is laid out along the first outer track. The first via plug is in contact with the end portion of the first line and extends between the first and second wiring layers, and the second via plug is in contact with the end portion of the second line and extends between the first and second wiring layers.

Abstract: There is provided a constant current driven oscillating circuit including: an oscillator with first and second ends; a first field effect transistor that turns ON when a signal of a lower level than a first threshold voltage is input to a first gate terminal, and outputs, from a second terminal, current that has been input from a first terminal; a second field effect transistor turning ON when a signal output from the oscillator and is at a higher level than a second threshold voltage is input to a second gate terminal connected to the second end of the oscillator, and outputs, from a fourth terminal, current that has been input from a third terminal connected to the second terminal and to the first end of the oscillator; and an adjusting section that adjusts the first threshold voltage according to the level of the signal output from the oscillator.

Abstract: A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed on the semiconductor functional devices such that the external connection pads are not connected to each other. The semiconductor device production process also includes measuring conductivity between the external connection pads.

Abstract: There is provided a constant current driven oscillating circuit including: an oscillator with first and second ends; a first field effect transistor that turns ON when a signal of a lower level than a first threshold voltage is input to a first gate terminal, and outputs, from a second terminal, current that has been input from a first terminal; a second field effect transistor turning ON when a signal output from the oscillator and is at a higher level than a second threshold voltage is input to a second gate terminal connected to the second end of the oscillator, and outputs, from a fourth terminal, current that has been input from a third terminal connected to the second terminal and to the first end of the oscillator; and an adjusting section that adjusts the first threshold voltage according to the level of the signal output from the oscillator.

Abstract: A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed on the semiconductor functional devices such that the external connection pads are not connected to each other. The semiconductor device production process also includes measuring conductivity between the external connection pads.

Abstract: Frequency multiplying circuitry includes a couple of integrator circuits. The one integrator circuit charges a capacitor with a larger time constant via a resistor when an input clock signal is in its high level and then discharges it with a smaller time constant when the clock signal is in its low level. The other integrator circuit charges and discharges its capacitor in the opposite manner to the one integrator circuit as to the level of the clock signal. An output circuit compares the output voltages of both integrator circuits with a reference voltage and raises the level of its output signal when either one of the output voltages drops below the reference voltage. The duty ratio of the circuitry is therefore little susceptible to the frequency of the input signal and power supply voltage.

Abstract: An output buffer circuit is provided for maintaining the slew rate of output waveforms of the output signal within a predetermined range regardless of changes of load on the output terminal. Series-connected feedback delay circuits (11-14) delay an input signal (IN) on the basis of the potential of an output signal (OUT) obtained through a feedback path (L1). Delay time of each feedback delay circuit varies according to load on an output terminal (2). Delay signals from the feedback delay circuits (11-14) are applied to one inputs of high-output selecting NAND gates (G11-G14), respectively. The NAND gates (G11-G14) also receive the input signal (IN) at their other inputs and output signals to gates of high output transistors (QP1-QP4), respectively. At the rise of the input signal (IN), the high output transistors (QP1-QP4) output the output signal (OUT) in response to the delay signals from the feedback delay circuits (11-14).

Abstract: Frequency multiplying circuitry includes a couple of integrator circuits. The one integrator circuit charges a capacitor with a larger time constant via a resistor when an input clock signal is in its high level and then discharges it with a smaller time constant when the clock signal is in its low level. The other integrator circuit charges and discharges its capacitor in the opposite manner to the one integrator circuit as to the level of the clock signal. An output circuit compares the output voltages of both integrator circuits with a reference voltage and raises the level of its output signal when either one of the output voltages drops below the reference voltage. The duty ratio of the circuitry is therefore little susceptible to the frequency of the input signal and power supply voltage.

Abstract: An output buffer circuit is provided for maintaining the slew rate of output waveforms of the output signal within a predetermined range regardless of changes of load on the output terminal. Series-connected feedback delay circuits (11-14) delay an input signal (IN) on the basis of the potential of an output signal (OUT) obtained through a feedback path (L1). Delay time of each feedback delay circuit varies according to load on an output terminal (2). Delay signals from the feedback delay circuits (11-14) are applied to one inputs of high-output selecting NAND gates (G11-G14), respectively. The NAND gates (G11-G14) also receive the input signal (IN) at their other inputs and output signals to gates of high output transistors (QP1-QP4), respectively. At the rise of the input signal (IN), the high output transistors (QP1-QP4) output the output signal (OUT) in response to the delay signals from the feedback delay circuits (11-14).