Patents by Inventor Kouji Soejima
Kouji Soejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9070754Abstract: The present invention prevents bumps on semiconductor chips from sticking to probe needles and coming off from the semiconductor chips. A wafer has effective areas where a plurality of bumps (first bumps) are formed. The bumps are formed on the side of an active surface of the semiconductor chips. The wafer further has non-effective areas where a plurality of dummy bumps are formed. Among the dummy bumps, some positioned at the outermost circumference are dummy bumps (second bumps) that are smaller than the other bumps. The dummy bumps (second bumps) intersect the inner peripheral edge of a shielding member as viewed in a plan view. The dummy bumps (second bumps) are formed over third pad electrodes. A bump-formation insulating film is removed from over the entire third pad electrodes.Type: GrantFiled: January 28, 2013Date of Patent: June 30, 2015Assignee: Renesas Electronics CorporationInventors: Akinori Yutani, Kouji Soejima
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Patent number: 8975150Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.Type: GrantFiled: July 25, 2011Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Patent number: 8552570Abstract: In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.Type: GrantFiled: January 6, 2009Date of Patent: October 8, 2013Assignee: Renesas Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Masaya Kawano, Kouji Soejima, Yoichiro Kurita
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Patent number: 8072073Abstract: A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed on the first wiring structure and having one or more second wiring layers, one or more second insulating layers, a second via and a third via; and an external terminal provided on the second wiring structure. The second via, which is connected to the second wiring layer of the second wiring structure and to the external terminal, has a connection interface disposed at an end of the via that is on the side of the external terminal.Type: GrantFiled: September 15, 2008Date of Patent: December 6, 2011Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Masaya Kawano, Kouji Soejima
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Publication number: 20110281401Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.Type: ApplicationFiled: July 25, 2011Publication date: November 17, 2011Applicants: C/O RENESAS ELECTRONICS CORPORATION, NEC CORPORATIONInventors: Kentaro MORI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Masaya KAWANO, Takehiko MAEDA, Kouji SOEJIMA
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Patent number: 8035217Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.Type: GrantFiled: June 9, 2008Date of Patent: October 11, 2011Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Publication number: 20110221071Abstract: In an electronic device having multilayer resin interconnection layers, it is desired to reduce the warp of its support substrate. It is manufactured by: forming a lower layer including a via and a first insulating part on the support substrate; and forming an intermediate layer including a first interconnection and a second insulating part covering the first interconnection on the lower layer. The lower layer is formed by: forming the first insulating part on a first circuit region and a first region surrounding it; and forming the via on the first circuit region. The intermediate layer is formed by: forming the first interconnection on the first circuit region; forming a film of the second insulation part to cover the lower layer; and removing the second insulating part on the first region such that an outer circumferential part of an upper surface of the lower layer part is exposed.Type: ApplicationFiled: March 10, 2011Publication date: September 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Norikazu MOTOHASHI, Kouji SOEJIMA, Yoichiro KURITA
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Patent number: 7999401Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.Type: GrantFiled: July 24, 2008Date of Patent: August 16, 2011Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Hideya Murai, Kentaro Mori, Shintaro Yamamichi, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Publication number: 20100314778Abstract: In forming a semiconductor device, an insulation layer is formed on top of a semiconductor chip having a plurality of external terminals. A plurality of interconnections is formed on the insulating layer. External terminals are electrically connected to coordinated interconnections through a plurality of vias formed in the insulation layer. The interconnections are each formed integral with a via conduction part which covers the entire surfaces of the bottom and the sidewall sections of the via. The interconnection is formed so as to be narrower in its region overlying the via than the upper via diameter.Type: ApplicationFiled: February 6, 2009Publication date: December 16, 2010Applicants: NEC CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Hideya Murai, Kentaro Mori, Shintaro Yamamichi, Masaya Kawano, Kouji Soejima
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Publication number: 20100295191Abstract: In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.Type: ApplicationFiled: January 6, 2009Publication date: November 25, 2010Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Masaya Kawano, Kouji Soejima, Yoichiro Kurita
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Publication number: 20090072404Abstract: A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed on the first wiring structure and having one or more second wiring layers, one or more second insulating layers, a second via and a third via; and an external terminal provided on the second wiring structure. The second via, which is connected to the second wiring layer of the second wiring structure and to the external terminal, has a connection interface disposed at an end of the via that is on the side of the external terminal.Type: ApplicationFiled: September 15, 2008Publication date: March 19, 2009Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Katsumi Kikuchi, Shintaro Yamamichi, Masaya Kawano, Kouji Soejima
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Publication number: 20090026636Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.Type: ApplicationFiled: July 24, 2008Publication date: January 29, 2009Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Hideya MURAI, Kentaro Mori, Shintaro Yamamichi, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Publication number: 20090001604Abstract: An oxide layer and a metal layer composed of a gold- or platinum-group metal are formed in the stated order on a substrate. A wiring body having a wiring layer, insulating layer, via, and electrode is formed on the metal layer. A semiconductor element is then connected as a flip chip via solder balls on the wiring body electrode, and underfill is introduced between the semiconductor element and the wiring body. Subsequently, a sealing resin layer is formed so as to cover the semiconductor element and the surface of the wiring body on which the semiconductor element is mounted, thus producing a semiconductor package. A high-density, detailed, thin semiconductor package can thereby be realized.Type: ApplicationFiled: March 1, 2006Publication date: January 1, 2009Inventors: Daisuke Tanaka, Shintaro Yamamichi, Hideya Murai, Tadanori Shimoto, Kaichirou Nakano, Katsumi Maeda, Katsumi Kikuchi, Yoichiro Kurita, Kouji Soejima
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Publication number: 20080303136Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.Type: ApplicationFiled: June 9, 2008Publication date: December 11, 2008Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima