Abstract: A microcontroller comprising a first memory 2 used by a CPU1 to perform arithmetic operations; a second memory 3 for a multitask process for storing data transferred from an external device 30 during the arithmetic process of CPU1; bus switches 4 and 5 for switching over the connection of data buses of CPU1 and the external device 30; and an address supply portion 7, which is connected to the address bus of the external device 30 while the second memory 3 is connected to the data bus of the external device 30, and which generates address signals by which to store data from the external device, wherein this microcontroller can perform a multitask process without adopting an expensive device such as a dual port RAM.

Abstract: A semiconductor memory circuit includes memory cells each having two storage semiconductor elements. One of these semiconductor elements is made inoperative in response to a first or a second operation control signal. This makes it possible to check the margin of a threshold voltage of the other storage semiconductor element at the time when writing, erasing and reading operations with respect thereto are being performed.

Abstract: An EEPROM circuit has two memory transistors in a memory cell of an array. Stored data is read out to a reading circuit via a first and second complementary bit lines. A writing circuit provides voltage to the cell so that the first memory transistor writes data and the second memory transistor erases data. An erasing circuit does the converse, i.e. provides voltage to the cell so that the first memory transistor erases data and the second memory transistor writes data.

Abstract: A test circuit for testing a programmable array of a microprocessor including an instruction register for receiving an instruction signal from a data bus in response to a control signal and for outputting the received instruction signal to output lines, and a programmable logic array having a plurality of NAND circuits each forming a conductive path between first and second terminals when a predetermined instruction signal is received thereby from the register. Each of the NAND circuits includes a first terminal, a second terminal and a plurality of MOSFETs each having a first, a second and a gate electrode with the gate electrode coupled to an output line of the instruction register, and with the first and second electrodes being connected in series between the respective first and second terminals.

Abstract: A nonvolatile memory system for one of a multiple of values includes a memory cell having an input terminal, an output terminal, and a control terminal. The memory cell, which may be an EEPROM, stores nonvolatile electric charge, and establishes a voltage threshold between the input terminal and the output terminal which influences a current therebetween, the threshold having a level which is dependent upon the amount of the electric charge stored by the storing means. A writing circuit is connected to the input terminal and is responsive to an input data signal having a value selected from among at least three values for applying electric charge, in an amount corresponding to the value of the selected data signal, to the input terminal for storage in the memory cell. A reading circuit is provided to measure the value of the voltage threshold between the input and output terminals and to output a data signal having a value which corresponds to the measured value of the threshold voltage.

Abstract: A random number generator built into an integrated circuit has at least one oscillator that generates clock pulses independent of the integrated circuit's system clock, at least two counters for counting those clock pulses, and read-out means for outputting the contents of the counters in response to a read signal. The random number generator accordingly has an extremely simple circuit configuration, but is capable of generating random numbers at a rapid rate.

Abstract: A microcomputer having a memory which stores coded instructions. An instruction register coupled to the memory is used for temporarily storing instructions one byte at a time. A programmable logic array is coupled to the register and has a decoder which decodes the bytes of the instruction in the register to provide control signals, the bytes of each instruction temporarily stored in the register producing control signals during each of at least first and second successive machine cycles.

Abstract: In an evaluation single-chip microcomputer which includes circuit elements connected to an internal bus and capable of storing data or of arithmetic operation, the contents of the circuit elements being required to be known outside of the microcomputer, a control circuit decodes instructions supplied through the internal bus and produces control signals for controlling the operations of the circuit elements, the data written in each of the circuit elements is transmitted to the internal bus during execution of any one of instructions involving transfer of data into the circuit element, and output terminals are provided for outputting part of the control signals from the control circuit and part of the output signals from the circuit elements through the internal bus, the control signals including write control signals for writing data in the circuit elements.

Abstract: A microcomputer selectively operable in a first mode or a second mode comprises a first read-only memory for storing a first program to be executed in the first mode, a second, programmable read-only memory for storing a second program to be executed in the second mode, an input circuit for inputting the second program to be written in the second read-only memory, an execution circuit for executing the first program or the second program, and a mode control circuit responsive to a mode selection signal for enabling execution of the first program when the mode selection signal designates the first mode and for enabling writing and execution of the second program when the mode selection signal designates the second mode.

Abstract: In a single-chip microcomputer having a first memory storing security data and a second memory for storing a test program. The test program includes test routines and a destruction routine to be executed prior to the test routines. The destruction routine destroys the security data in the first memory.

Abstract: A programmable logic array circuit which has a decoder, a sense amplifier and a latching circuit. The decoder decodes an instruction code into an output signal after a first precharge timing. The latching circuit latches the output signal from the decoder immediately before a second precharge timing. The gate circuit controls an output operation of the latching circuit in response to a prescribed timing signal.

Abstract: In an evaluation single-chip microcomputer which includes circuit elements connected to an internal bus and capable of storing data or of arithmetic operation, the contents of the circuit elements being required to be known outside of the microcomputer, a control circuit decodes instructions supplied through the internal bus and produces control signals for controlling the operations of the circuit elements, the data written in each of the circuit elements is transmitted to the internal bus during execution of any one of instructions involving transfer of data into the circuit element, and output terminals are provided for outputting part of the control signals from the control circuit and part of the output signals from the circuit elements through the internal bus, the control signals including write control signals for writing data in the circuit elements.

Abstract: In a computer having a program including a first type of instruction and a second type of instruction, a program memory has a first area for storing the first type of instruction and a second area for storing the second type of instruction. An address code is supplied from a program counter to the program memory, which thereby produces an instruction code stored at the addressed memory location. A control unit is responsive to the instruction code from the program memory for producing a control signal for controlling the operation of the computer. A protection circuit is provided for preventing execution of the first type of instruction when the address code output from the program counter does not designate any memory location in the first area.

Abstract: In a computer, an address value is transferred to data pointer and a data is transfered from a memory location of a data memory being designated by the address value in the data pointer to a temporary register, the transfer of the address value and the transfer of the data being conducted within a first instruction cycle. In a second instruction cycle immediately following the first instruction cycle, an operation is performed by an ALU on data in an accumulater and the temporary register, and the result of operation is transferred to the accumulator and to the memory location of the data memory being designated by the data pointer.

Abstract: A reset circuit for a logic circuit comprises a MOS transistor having a gate coupled to a power supply, a source receiving a reset input and a drain whose potential is high when the reset input is high and the power supply voltage drops below a predetermined threshold, a flip-flop connected to be set when the drain of the MOS transistor is high and reset when the reset input is low, and a circuit producing a reset output when the flip-flop is in the set state, the reset output being applied to the logic circuit.

Abstract: A watchdog timer for monitoring the operation of a computer monitors if the period of a writing signal (W.sub.T) generated by each execution of an instruction of a program is within the predetermined duration. The present watchdog timer comprises a register (2) for storing predetermined DATA upon receipt of the writing signal (W.sub.T), a counter (4) which is incremented by a clock pulse (.phi.), a comparator (3) for providing coincidence output signal when content of the counter reaches said predetermined DATA in the register (2), a first flip-flop (F.sub.1) for storing said coincidence output signal for one period of said clock pulse (.phi.), a second flip-flop (F.sub.2) for storing said coincidence output signal upon receipt of said clock pulse (.phi.), a third flip-flop (F.sub.3) for storing output of said second flip-flop (F.sub.2) upon receipt of said clock pulse (.phi.), an AND circuit (G.sub.1) for providing logical product of reverse output (Q.sub.1) of said first flip-flop (F.sub.