Abstract: A semiconductor device including a first switch coupled to a first power supply line, a second switch coupled to the first switch and to a second power supply line, and a storage part provided in a path which is between the second power supply line and the first switch, and having a high resistance state and a low resistance state, and wherein the first switch is turned on and the second switch is turned off when a resistance state of the storage part is in a high resistance state.

Abstract: A semiconductor device includes a first memory unit, a second memory unit, and a determination unit receiving a first signal permitting a write operation to one of the first memory unit and the second memory unit, and a second signal indicating whether the write operation of information to the first memory unit is finished, wherein the determination unit outputs a signal prohibiting a write operation to the second memory unit, if the second signal indicates the write operation of the information is finished.

Abstract: A semiconductor device including a first switch coupled to a first power supply line, a second switch coupled to the first switch and to a second power supply line, and a storage part provided in a path which is between the second power supply line and the first switch, and having a high resistance state and a low resistance state, and wherein the first switch is turned on and the second switch is turned off when a resistance state of the storage part is in a high resistance state.

Abstract: A semiconductor device includes a first memory unit, a second memory unit, and a determination unit receiving a first signal permitting a write operation to one of the first memory unit and the second memory unit, and a second signal indicating whether the write operation of information to the first memory unit is finished, wherein the determination unit outputs a signal prohibiting a write operation to the second memory unit, if the second signal indicates the write operation of the information is finished.

Abstract: A semiconductor integrated circuit for reducing power consumption and simultaneous switching noise in an output circuit, which outputs plural pieces of output data including first and second output data, each including a plurality of bits. The first output data is generated from first original data. The second output data is generated from second original data. A comparison circuit generates a determination signal indicating whether the number of changed bits of the second original data from the first original data is greater than a predetermined number. In accordance with the determination signal, a selection circuit generates output data expressing the second original data and the data type in a first expression format or output data expressing the complement data of the second original data and the data type in a second expression format. This is output as the second output data.

Abstract: A semiconductor integrated circuit for reducing power consumption and simultaneous switching noise in an output circuit, which outputs plural pieces of output data including first and second output data, each including a plurality of bits. The first output data is generated from first original data. The second output data is generated from second original data. A comparison circuit generates a determination signal indicating whether the number of changed bits of the second original data from the first original data is greater than a predetermined number. In accordance with the determination signal, a selection circuit generates output data expressing the second original data and the data type in a first expression format or output data expressing the complement data of the second original data and the data type in a second expression format. This is output as the second output data.

Abstract: A semiconductor integrated circuit and a method of controlling the semiconductor integrated circuit are capable of performing low power consumption and an improvement in the operation speed. A variable higher reference voltage and a variable lower reference voltage are outputted from a voltage generator. The variable higher reference voltage is applied to a source terminal of a PMOS transistor, and the variable lower reference voltage is applied to a source terminal of an NMOS transistor. The variable higher reference voltage and the variable lower reference voltage are variably controlled in such a manner that a threshold voltage becomes large in the case where power saving is going to be conducted in an operation standby state or the like, and variably controlled in such a manner that the threshold voltage becomes small in the case where a processing speed is required during the operation or the like.

Abstract: A semiconductor device includes multi-pin I/O buffers. The I/O buffers are located near an I/O pad area of the device. The multi-pin I/O buffers include multiple, generally L-shaped terminals that are connected to pads in the I/O pad area with wirings. The terminals of the I/O buffers include a horizontal terminal section and a vertical terminal section. The horizontal terminal sections extend in a width direction from a corner of the buffer toward a middle point of a side of the buffer, and the vertical terminal section extends in a length direction from the corner of the terminal toward a middle point of a side of the buffer. The wirings may also be generally L-shaped.