Patents by Inventor Koujiro Kameyama
Koujiro Kameyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8669183Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.Type: GrantFiled: May 18, 2007Date of Patent: March 11, 2014Assignees: SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Akira Suzuki, Katsuyuki Seki, Koujiro Kameyama, Takahiro Oikawa
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Patent number: 8278213Abstract: This invention improves reliability of a semiconductor device and a manufacturing method thereof. A glass substrate is bonded on a surface of a silicon wafer formed with pad electrodes. Next, via holes are formed from a back surface of the silicon wafer to pad electrodes, and a groove is formed extending along a center line of a dicing line and penetrating the silicon wafer from its back surface. After then, in processes including heating treatment, cushioning pads, wirings, a solder mask, and solder balls are formed on the back surface of the silicon wafer. Finally, the silicon wafer bolstered by the glass substrate is separated into individual silicon dice by dicing.Type: GrantFiled: February 10, 2005Date of Patent: October 2, 2012Assignee: SANYO Electric Co., Ltd.Inventors: Koujiro Kameyama, Akira Suzuki, Yoshio Okayama
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Patent number: 8227901Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.Type: GrantFiled: June 11, 2009Date of Patent: July 24, 2012Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Katsuyuki Seki, Akira Suzuki, Keita Odajima, Kikuo Okada, Koujiro Kameyama
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Patent number: 8187949Abstract: When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form groove portions 4 therein, and in this state, the front surface of the wafer 2a is attached to a supporting body 5 having rigidity with an adhesive layer 6. Then, the wafer 2a is ground from the back surface and diced into individual dies 2b, and then a back surface process including a heat treatment such as the formation of back surface electrodes 9a is performed in the state where the dies 2b are attached to the supporting body 5.Type: GrantFiled: March 12, 2008Date of Patent: May 29, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Koujiro Kameyama
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Patent number: 8173543Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.Type: GrantFiled: July 26, 2007Date of Patent: May 8, 2012Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Katsuyuki Seki, Akira Suzuki, Koujiro Kameyama, Takahiro Oikawa
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Patent number: 8148788Abstract: The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N? type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.Type: GrantFiled: August 10, 2009Date of Patent: April 3, 2012Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Akira Suzuki, Naofumi Tsuchiya, Koujiro Kameyama
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Patent number: 8076755Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: GrantFiled: June 6, 2008Date of Patent: December 13, 2011Inventors: Mitsuo Umemoto, Shigehito Matsumoto, Hirotoshi Kubo, Yukari Shirahata, Masamichi Yamamuro, Koujiro Kameyama
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Patent number: 7795115Abstract: The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.Type: GrantFiled: December 27, 2006Date of Patent: September 14, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd.Inventors: Koujiro Kameyama, Akira Suzuki, Takahiro Oikawa
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Patent number: 7772043Abstract: A semiconductor device with plating film layers for semiconductor device leads is described. A first plating film layer that includes Sn as a main material is formed on a semiconductor device lead in which Cu or Fe—Ni is a main material. The outermost surface of the lead includes a plating film layer in which Sn—Bi is the main material. The plating film layer is formed from a plating liquid in which Bi is introduced from a lead hold means. The Bi content relative to Sn in the first plating film layer is approximately 0 wt. % to 1 wt. %.Type: GrantFiled: March 28, 2007Date of Patent: August 10, 2010Assignee: Sanyo Electric Co., Ltd.Inventor: Koujiro Kameyama
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Patent number: 7750478Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.Type: GrantFiled: June 12, 2007Date of Patent: July 6, 2010Assignees: Sanyo Electric Co., Ltd., Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, NEC CorporationInventors: Koujiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto, Kenji Takahashi, Hiroshi Terao, Masataka Hoshino
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Patent number: 7732925Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.Type: GrantFiled: February 11, 2005Date of Patent: June 8, 2010Assignees: SANYO Electric Co., Ltd., Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, NEC CorporationInventors: Yoshio Okayama, Akira Suzuki, Koujiro Kameyama, Mitsuo Umemoto, Kenji Takahashi, Hiroshi Terao, Masataka Hoshino
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Patent number: 7728438Abstract: An optical semiconductor device of which the moisture resistance and the like are improved and the manufacturing method thereof are provided. An optical semiconductor device of the embodiment is configured to include an optical semiconductor element on a surface of which a circuit portion including a light-receiving or light-emitting element is formed; a terminal portion which is provided on a back of the optical semiconductor element and electrically connected with the circuit portion; a covering layer which covers the surface of the optical semiconductor element and is made of a transparent material; and sealing resin which covers side faces of the covering layer and of the optical semiconductor element. The circuit portion and the terminal portion may be connected by a rewiring pattern.Type: GrantFiled: September 29, 2006Date of Patent: June 1, 2010Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Koujiro Kameyama, Kiyoshi Mita
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Publication number: 20100052090Abstract: The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N? type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.Type: ApplicationFiled: August 10, 2009Publication date: March 4, 2010Applicants: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., SANYO Electric Co., LtdInventors: Akira Suzuki, Naofumi Tsuchiya, Koujiro Kameyama
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Publication number: 20100044873Abstract: When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form groove portions 4 therein, and in this state, the front surface of the wafer 2a is attached to a supporting body 5 having rigidity with an adhesive layer 6. Then, the wafer 2a is ground from the back surface and diced into individual dies 2b, and then a back surface process including a heat treatment such as the formation of back surface electrodes 9a is performed in the state where the dies 2b are attached to the supporting body 5.Type: ApplicationFiled: March 12, 2008Publication date: February 25, 2010Applicants: Sanyo Electric Co., Ltd, Sanyo Semiconductor co., LtdInventor: Koujiro Kameyama
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Publication number: 20090309194Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.Type: ApplicationFiled: June 11, 2009Publication date: December 17, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.Inventors: Katsuyuki SEKI, Akira Suzuki, Keita Odajima, Kikuo Okada, Koujiro Kameyama
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Patent number: 7566588Abstract: To provide a semiconductor device 10, which is thin, compact, and excellent in mechanical strength and humidity resistance. Semiconductor device 10A has a configuration such that in semiconductor device 10A, wherein an optical semiconductor element 14, having a light receiving part or a light emitting part, is sealed in a sealing resin 13, a cover layer 12, covering the top surface of optical semiconductor element 14, is exposed from the top surface of sealing resin 13. Thus in comparison to a related-art example with which the entirety is sealed by a transparent resin, sealing resin 13 can be formed thinly and the thickness of the entire device can be made thin. Furthermore, semiconductor device 10 is arranged using a sealing resin having a filler mixed in. A semiconductor device that is excellent in mechanical strength and humidity resistance can thus be arranged.Type: GrantFiled: October 13, 2006Date of Patent: July 28, 2009Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Koujiro Kameyama, Kiyoshi Mita
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Publication number: 20080237808Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: ApplicationFiled: June 6, 2008Publication date: October 2, 2008Applicants: Sanyo Electric Co., Ltd., Kanto Semiconductors Co., Ltd.Inventors: Hirotoshi Kubo, Yukari Shirahata, Shigehito Matsumoto, Masamichi Yamamuro, Koujiro Kameyama, Mitsuo Umemoto
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Patent number: 7397128Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: GrantFiled: March 28, 2006Date of Patent: July 8, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Hirotoshi Kubo, Yukari Shirahata, Shigehito Matsumoto, Masamichi Yamamuro, Koujiro Kameyama, Mitsuo Umemoto
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Publication number: 20080023846Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.Type: ApplicationFiled: July 26, 2007Publication date: January 31, 2008Applicants: SANYO ELECTRIC CO., LTD., Sanyo Semiconductor Co., Ltd.Inventors: Katsuyuki Seki, Akira Suzuki, Koujiro Kameyama, Takahiro Oikawa
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Publication number: 20070281474Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.Type: ApplicationFiled: May 18, 2007Publication date: December 6, 2007Applicants: Sanyo Electric Co., Ltd.Inventors: Akira Suzuki, Katsuyuki Seki, Koujiro Kameyama, Takahiro Oikawa