Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract: A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode, and an intermediate electrode arranged between the upper electrode and the lower electrode, and arranged adjoining to the first capacitor. In the first capacitor and the second capacitor, the upper electrode, the lower electrode and the shield line are electrically connected to a ground electrode. The shield line lies between the first capacitor and the second capacitor. Accordingly, a MIM capacitor with excellent layout efficiency is provided while noise effects are reduced.

Abstract: A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode, and an intermediate electrode arranged between the upper electrode and the lower electrode, and arranged adjoining to the first capacitor. In the first capacitor and the second capacitor, the upper electrode, the lower electrode and the shield line are electrically connected to a ground electrode. The shield line lies between the first capacitor and the second capacitor. Accordingly, a MIM capacitor with excellent layout efficiency is provided while noise effects are reduced.

Abstract: A semiconductor device includes a MIM capacitor that includes an insulating film and a first electrode and a second electrode which are formed in the same layer in the insulating film and are facing to each other with the insulating film interposed therebetween. The first electrode and the second electrode respectively include a first high aspect via and a second high aspect via which extend as long as a length, in a stacked direction of the substrate, of a via and an interconnect provided on the via so as to be connected to the via formed in another region. A first potential and a second potential are respectively supplied to the first electrode and the second electrode.

Abstract: In view of micronizing semiconductor device and of suppressing current leakage in a shared contact allowing contact between a gate electrode and an impurity-diffused region, a semiconductor device 100 includes a first gate electrode 108, a fourth source/drain region 114b, and a shared contact electrically connecting the both, wherein in a section taken along the gate length direction, the first gate electrode 108 and the fourth source/drain region 114b are disposed as being apart from each other, an element-isolating insulating film 102 is formed over the entire surface of a semiconductor substrate 160 exposed therebetween, and the distance between the first gate electrode 108 and the fourth source/drain region 114b is made substantially equal to the width of the sidewall formed on the side face of the first gate electrode 108, when viewed in another section taken along the gate length direction.

Abstract: In view of micronizing semiconductor device and of suppressing current leakage in a shared contact allowing contact between a gate electrode and an impurity-diffused region, a semiconductor device 100 includes a first gate electrode 108, a fourth source/drain region 114b, and a shared contact electrically connecting the both, wherein in a section taken along the gate length direction, the first gate electrode 108 and the fourth source/drain region 114b are disposed as being apart from each other, an element-isolating insulating film 102 is formed over the entire surface of a semiconductor substrate 160 exposed therebetween, and the distance between the first gate electrode 108 and the fourth source/drain region 114b is made substantially equal to the width of the sidewall formed on the side face of the first gate electrode 108, when viewed in another section taken along the gate length direction.