Abstract: A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area.

Abstract: A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area.

Abstract: A technique which prevents cracking in a solder resist layer covering an interposer surface between external coupling terminals of an interconnection substrate, thereby reducing the possibility of interconnect wire disconnection resulting from such cracking. A semiconductor package is mounted over an interconnection substrate. An underfill resin layer seals the space between the semiconductor package and the interconnection substrate. External coupling terminals, interconnect wires and a solder resist layer are formed over the surface of an interposer (constituent of the semiconductor package) where the semiconductor chip is not mounted. In an area where an interconnect wire passing between two neighboring ones of the external coupling terminals intersects with a line connecting the centers of the two external coupling terminals, the interconnect wire is not covered by the solder resist layer.

Abstract: A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.

Abstract: A technique which prevents cracking in a solder resist layer covering an interposer surface between external coupling terminals of an interconnection substrate, thereby reducing the possibility of interconnect wire disconnection resulting from such cracking. A semiconductor package is mounted over an interconnection substrate. An underfill resin layer seals the space between the semiconductor package and the interconnection substrate. External coupling terminals, interconnect wires and a solder resist layer are formed over the surface of an interposer (constituent of the semiconductor package) where the semiconductor chip is not mounted. In an area where an interconnect wire passing between two neighboring ones of the external coupling terminals intersects with a line connecting the centers of the two external coupling terminals, the interconnect wire is not covered by the solder resist layer.

Abstract: A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.