Abstract: According to the boundary detector of this invention, in order to perform high-speed boundary detection processing for image data read out from a frame memory comprising a plurality of memory planes, image data having a predetermined unit data length, at identical positions from the plurality of memory planes in the frame memory, are compared, by a comparator, with input boundary condition data for a corresponding one of the plurality of memory planes, to produce boundary data. By using all the boundary data, a boundary bit position is detected according to input detection mode designation data, and boundary bit position data representing a detected boundary bit position is output. The boundary detector further includes a generator for generating the boundary data when it is used in boundary detection processing. However, when the boundary data is not used for this purpose, mask data selected on the basis of the memory plane designation data is output as the boundary data, by the generator.

Abstract: A bit map display apparatus of this invention includes a bit map memory consisting of a plurality of memory planes, a display controller which can output a window number indicating a displaying window in accordance with display scan, a register, arranged for each plane, for holding bit data for designating a display enable/disable state in units of windows, a selector, arranged for each plane, for selecting one bit of output data from the corresponding register as a mask bit in accordance with the window number indicated by the display controller, and a gate circuit, arranged for each plane, for controlling data read out from the corresponding plane in accordance with the mask bit.

Abstract: An image data processing apparatus for processing image data in a pipe line fashion includes an access controller for selectively generating addresses and control data in synchronism with a memory cycle in response to a start command, and for selectively and separately outputting the addresses onto address buses and the control data onto control buses.

Abstract: A bit map image processing apparatus includes a window detector for detecting a window position on a screen and a frame memory for storing image data. The frame memory has p 2-port memories each having an l bits.times.m (column).times.n (row) memory area. Each row of the two-dimensional memory area of the frame memory is divided and managed in units of l.multidot.p bits.

Abstract: A priority controller includes a pair of read only memories and a register. The register stores information identifying a request circuit to which priority has recently been granted. Corresponding locations of the two read only memories store identical data for determining priority. These read only memories are alternately enabled in accordance with the value of the most significant bit position of the information stored in the register. One of the read only memories is addressed by a first address signal consisting of the lower two bits of the register information and request signals REQ0-REQ7 supplied from eight request circuits. The other of the two read only memories is addressed by a second address obtained by exchanging the positions of the signals REQ0-REQ3 of the first address with signals REQ4-REQ7 of this first address. The information produced by the read only memory which is enabled indicates the request circuit to which priority is to be granted.

Abstract: A data processing system with a condition data setting function is provided. In the system, a microprogram memory designed stores a plurality of specific subtraction micro-instructions for obtaining condition data consisting of a combination of bits respectively representing the sign of the results of each of a plurality of substraction operations. A micro-instruction read out from said microprogram memory is loaded into a micro-instruction register. An arithmetic and logic section performs an arithmetic operation, in accordance with the specific subtraction micro-instructions loaded in said micro-instruction register, and outputs status data including a carry flag and a sign flag. A multiplexer selects the carry flag or sign flag, in accordance with the first specific bit of the specific subtraction micro-instruction loaded in said micro-instruction register.