Abstract: A video output controller has a video output buffer, a DMA controller, and a display controller. The display controller has a DMA command list processor configured to determine which of the DMA commands contained in the DMA command list must be issued, an initialize signal port configured to receive an initialize signal for starting initialization, a step signal port configured to receive a step signal for starting the issuance of the DMA command, and an external signal processor configured to provide the DMA command list processor with a timing signal for issuing a DMA command according to the initialize signal and step signal .

Abstract: A video output controller has a video output buffer, a DMA controller, and a display controller. The display controller has a DMA command list processor configured to determine which of the DMA commands contained in the DMA command list must be issued, an initialize signal port configured to receive an initialize signal for starting initialization, a step signal port configured to receive a step signal for starting the issuance of the DMA command, and an external signal processor configured to provide the DMA command list processor with a timing signal for issuing a DMA command according to the initialize signal and step signal.

Abstract: When an error is detected in a received packet, a higher application is informed that the error occurred, and when no error is detected in the received packet, the higher application is informed that the packet has been received. If a next packet is received while a packet having the detected error is stored in a data storing region, an acknowledge signal indicating that the packet cannot be received is sent to a source node, and the packet having the detected error stored in the data storing region is invalidated by a request from the higher application. When the error is detected in a received packet, that packet stored in the data storing region is invalidated.