Abstract: This neural network generating device for generating a neural network execution model for computing a neural network is provided with: an execution model generating unit for generating the neural network execution model on the basis of hardware information relating to hardware on which the neural network execution model operates, and network information relating to the neural network; and a learning unit for generating trained parameters of the generated neural network execution model.

Abstract: A neural network circuit comprising a convolution operation circuit that performs a convolution operation on input data; a quantization operation circuit that performs a quantization operation on convolution operation output data from the convolution operation circuit; and a command fetch unit that reads, from an external memory, commands for operating the convolution operation circuit or the quantization operation circuit.

Abstract: A method for controlling a neural network circuit that is provided with a first memory, a convolution operation circuit that performs a convolution operation, a second memory, a quantization operation circuit, a second write semaphore, a second read semaphore, a third write semaphore, and a third read semaphore, wherein the method for controlling the neural network circuit involves making the convolution operation circuit implement a convolution operation based on the third read semaphore and the second write semaphore.

Abstract: A neural network circuit that can be embedded in an embedded device such as an IoT device, and that provides high performance. The neural network circuit includes a first memory unit that stores input data; a convolution operation circuit that performs a convolution operation on a weight and the input data stored in the first memory unit; a second memory unit that stores convolution operation output data from the convolution operation circuit; and a quantization operation circuit that performs a quantization operation on the convolution operation output data stored in the second memory unit; wherein the first memory unit stores a quantization operation output data from the quantization operation circuit; and the convolution operation circuit performs the convolution operation on the quantization operation output data stored in the first memory unit as the input data.

Abstract: The present invention presents an image processing apparatus that performs rotation, enlargement, reduction, clipping or overlapping processing of images at high speed using low capacity memories instead of page memories and without the need to read image data in repetition. A first band data storing element receives input image data line by line and stores it as local data. The local data stored in the first band data storing element is transformed by local data transforming element and then stored in a transformed data storing element. The local data is then read in the order it is to be output and stored in a second band data storing element. An image output element then outputs the local data as an output image.

Abstract: The present invention presents an image processing apparatus that performs rotation, enlargement, reduction, clipping or overlapping processing of images at high speed using low capacity memories instead of page memories and without the need to read image data in repetition. A first band data storing element receives input image data line by line and stores it as local data. The local data stored in the first band data storing element is transformed by local data transforming element and then stored in a transformed data storing element. The local data is then read in the order it is to be output and stored in a second band data storing element. An image output element then outputs the local data as an output image.

Abstract: The present invention provides a variable-length code decoder for inputting a code data bit string having a predetermined number of code data bits in every decoding cycle and decoding it, which comprises storing means for storing a decoded symbol and a node in a code tree in the next decoding cycle corresponding to each combination of a value of the code data bit string and a node in the code tree, reading means for reading the decoded symbol and the node in the code tree in the next decoding cycle from the storing means in accordance with the code data bit string inputted in a current decoding cycle and the node in the code tree in the current decoding cycle, outputting means for outputting the decoded symbol read by the reading means, and providing means for providing the node in the code tree in the next decoding cycle read by the reading means to the reading means.