Patents by Inventor Kounosuke TATEISHI

Kounosuke TATEISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11676870
    Abstract: A stacked-layer body including a gate insulating film and a control gate electrode is formed in a product region and a scribe region. Next, a gate insulating film and a conductive film are so formed that the stacked-layer body is covered. Next, an etching process is so performed to the conductive film that an upper surface of the conductive film is lower than that of an upper surface of the stacked-layer body, thereby forming a measurement pattern in the scribe region. Next, a memory gate electrode is formed by patterning the conductive film in the product region. Next, a silicide layer is formed on an upper surface of the memory gate electrode in the product region in a state where an upper surface of the measurement pattern is covered by an insulating film. Next, a resistance value of the measurement pattern covered by the insulating film is measured.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: June 13, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kounosuke Tateishi, Hiroaki Mizushima
  • Publication number: 20220093618
    Abstract: A stacked-layer body including a gate insulating film and a control gate electrode is formed in a product region and a scribe region. Next, a gate insulating film and a conductive film are so formed that the stacked-layer body is covered. Next, an etching process is so performed to the conductive film that an upper surface of the conductive film is lower than that of an upper surface of the stacked-layer body, thereby forming a measurement pattern in the scribe region. Next, a memory gate electrode is formed by patterning the conductive film in the product region. Next, a silicide layer is formed on an upper surface of the memory gate electrode in the product region in a state where an upper surface of the measurement pattern is covered by an insulating film. Next, a resistance value of the measurement pattern covered by the insulating film is measured.
    Type: Application
    Filed: September 16, 2021
    Publication date: March 24, 2022
    Inventors: Kounosuke TATEISHI, Hiroaki MIZUSHIMA