Patents by Inventor Kousaku Hirose

Kousaku Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor gate array device
    Patent number: 6160275
    Abstract: In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: December 12, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoji Nishio, Yasuo Kaminaga, Isamu Kobayashi, Yoshihiko Yamamoto, Nozomi Horino, Kousaku Hirose