Abstract: A layer forming material is a compound which has a structure of six-membered ring coordinated to Cu and containing Si, and of which general formula is represented by the following chemical formula: ##STR1## wherein X.sub.1 and X.sub.2 are elements of the VI group of the same or different types which are coordinate-bonded to Cu, and of which examples include O, S, Se, Te and the like, at least one of Y.sub.1, Y.sub.2 and Y.sub.3 is Si, L is a group which has a double or triple bond and which is able to supply electrons to Cu, and each of R.sub.1 and R.sub.2 is any of SiF.sub.3, SiH.sub.3, CF.sub.3 and CH.sub.3 for example.

Abstract: An integrated circuit having a multi-layered metal wiring structure with interlayer insulating films therebetween. A small cutout is made in a metal wiring when it is desirous to have the metal wiring touch a contact formed in a through hole passing through said cutout. A larger cutout is made in a metal wiring when it is desirous to have the metal wiring remain spaced from a contact formed in a through hole passing through said cutout.

Abstract: A first electrode and a first insulating layer of electrode insulation are formed on a first semiconductor substrate. A second electrode and a second insulating layer of electrode insulation are formed on a second semiconductor substrate. The first semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement. Likewise, the second semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement, wherein the pattern of the second semiconductor substrate has a phase shift of 180 degrees with respect to the pattern of the first semiconductor substrate. The first and second semiconductor substrates are bonded together with their patterns in engagement.

Abstract: There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed.

Abstract: A first metallization layer is locally formed on the surface of a semiconductor substrate thereby leaving portions of the semiconductor substrate's surface exposed. A first silicon oxide layer is then formed in such a manner that it covers the exposed portions of the semiconductor substrate's surface and the first metallization layer. This is followed by the formation of an HMDS molecular layer on the first silicon oxide layer. Then, a second silicon oxide is formed on the molecular layer by means of a CVD process utilizing the chemical reaction of ozone with TEOS. Finally, a second metallization layer is locally formed on the second silicon oxide layer.

Abstract: On an insulating substrate are formed first aluminum interconnections. In openings formed in a silicon dioxide film are formed unit cells each consisting of a tungsten electrode and an aluminum alloy electrode containing silicon. Over the silicon dioxide film are formed a large number of linear second aluminum interconnections which are orthogonal to the first aluminum interconnections. At the individual intersections of the first and second aluminum interconnections are disposed the unit cells so as to compose a memory cell array. When a large current is allowed to flow through the unit cell, silicon in the aluminum alloy electrode moves in a direction opposite to the current flow and is precipitated in the aluminum electrode in the vicinity of the interface with the tungsten electrode, resulting in an increase in resistance value. When a large current is allowed to flow through the unit cell in the opposite direction, silicon is diffused, resulting in a reduction in resistance value.

Abstract: The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.

Abstract: On an insulating substrate are formed first aluminum interconnections. In openings formed in a silicon dioxide film are formed unit cells each consisting of a tungsten electrode and an aluminum alloy electrode containing silicon. Over the silicon dioxide film are formed a large number of linear second aluminum interconnections which are orthogonal to the first aluminum interconnections. At the individual intersections of the first and second aluminum interconnections are disposed the unit cells so as to compose a memory cell array. When a large current is allowed to flow through the unit cell, silicon in the aluminum alloy electrode moves in a direction opposite to the current flow and is precipitated in the aluminum electrode in the vicinity of the interface with the tungsten electrode, resulting in an increase in resistance value. When a large current is allowed to flow through the unit cell in the opposite direction, silicon is diffused, resulting in a reduction in resistance value.

Abstract: A BPSG layer serving as a silicon oxide layer is formed on a semiconductor substrate 1. Formed on the surface of the BPSG layer is a hydrophobic molecular layer comprising hydrophobic groups such as methyl, ethyl and the like, by a silylation reaction (in which silyl having hydrophobic groups such as methyl groups, ethyl groups and the like, is reacted with OH groups, and in which the hydrophobic groups are substituted with H of the OH groups to generate --O--Si(CH.sub.3).sub.3 or the like). The molecular layer prevents the BPSG layer from absorbing moisture.

Abstract: A silicon dioxide film is partly etched away to form an opening thereby exposing a silicon substrate. The surface of the opening, which is almost entirely covered with Si-OH, is coated with hexamethyldisilazane (HMDS) to bring about a silylation reaction. This causes the silicon substrate surface to be covered with a molecular film formed by replacing the hydrogen part in Si-OH with Si((CH.sub.3).sub.3. Atoms of aluminum are ejected by a sputtering process. The ejected aluminum atoms collide with the molecular film. Although some hydrocarbons (CH.sub.x) are sputtered or ejected due to such collision, a SiO.sub.x C.sub.y H.sub.z film 12' transformed from the molecular film is left between an aluminum film deposited and the silicon substrate. This SiO.sub.x C.sub.y H.sub.z film 12' acts as a barrier metal. The presence of the SiO.sub.x C.sub.y H.sub.z film prevents the occurrence of counter diffusion in the Al-Si system. No spikes are formed as a result.

Abstract: Metal wires are formed side by side over a semiconductor substrate, with an interlayer insulating film interposed between the metal interconnections and the semiconductor substrate. The metal interconnections are covered with a passivation film composed of a lower silicon oxide film and an upper silicon nitride film. The silicon oxide film is deposited so that the maximum thickness of the portions of the silicon oxide film on the side faces of the metal interconnections is less than half of the minimum space between the metal interconnections. The silicon nitride film is deposited so as to be interposed between the portions of the silicon oxide film on the side faces of the adjacent metal interconnections.

Abstract: A forming apparatus of a thin film includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate. A feeding device is provided in the processing chamber for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film includes the steps of forming the thin film on the surface of the supplied substrate in the processing chamber, and feeding material for forming the organic molecular layer, including silicon or germanium, on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.

Abstract: After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion.

Abstract: According to the method of preventing the corrosion of metallic wirings of the present invention, aluminium alloy wirings are formed on the surface of a substrate with the use of photoresists, and the photoresists are then removed. Thereafter, HMDS (hexamethyl disilazine) serving as a surface-active agent or its derivative is supplied to the aluminium alloy wirings to form hydrophobic molecular layers on the lateral walls of the aluminium alloy wirings.

Abstract: Disclosed is a method for fabricating an interconnection structure comprising a step of depositing an Al or Al alloy film on a dielectric film by a sputtering method improved in step coverage, a step of processing said Al or Al alloy film or a layered metal film thereof with another metal film into a metal line, and a step of depositing a film of high melting point metal or alloy thereof on the top and side surfaces of said line.

Abstract: A stripe-color filter for spatial color encoding in a color TV camera, having a striped semiconductor filter-element-layer supported between a transparent substrate layer and a transparent dielectric covering layer. There are further provided a first coating layer of a transparent thin film between the substrate layer and the semiconductor filter-element-layer and a second coating layer of a transparent thin film between the semiconductor filter-element-layer and the covering layer. The refractive indexes of those layers are in the relationship: n.sub.F >n.sub.T1 >n.sub.S and n.sub.F >n.sub.T2 >n.sub.D, wherein n.sub.S represents the refractive index of the substrate layer, n.sub.T1 the first coating layer, n.sub.F the semiconductor filter-element-layer, n.sub.D the covering layer, and n.sub.T2 the second coating layer.