Patents by Inventor Kousei Ushijima

Kousei Ushijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7786005
    Abstract: An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: August 31, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kenichi Yamamoto, Masashige Moritoki, Takashi Shimane, Kazumi Saito, Hiroaki Tomimori, Takamasa Itou, Kousei Ushijima, Katsuro Tateyama
  • Patent number: 7510967
    Abstract: The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal interconnect on a substrate; forming a refractory metal layer containing titanium (Ti) or tantalum (Ta) on a surface of the metal interconnect; forming an insulating interlayer so as to cover the refractory metal layer; selectively etching the insulating interlayer with an etchant gas containing an organic fluoride to form a hole, in which the refractory metal layer is exposed; treating an interior of the hole with an organic chemical solution to remove fluorinated compounds of Ti or Ta while leaving fluorocarbons on the surface of the refractory metal layer, the fluorinated compounds of Ti or Ta and the fluorocarbons being created during the etching step and present in the interior of the hole; and performing plasma-treatment for the interior of said hole to remove the fluorocarbon.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: March 31, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kousei Ushijima
  • Publication number: 20070275558
    Abstract: The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal interconnect on a substrate; forming a refractory metal layer containing titanium (Ti) or tantalum (Ta) on a surface of the metal interconnect; forming an insulating interlayer so as to cover the refractory metal layer; selectively etching the insulating interlayer with an etchant gas containing an organic fluoride to form a hole, in which the refractory metal layer is exposed; treating an interior of the hole with an organic chemical solution to remove fluorinated compounds of Ti or Ta while leaving fluorocarbons on the surface of the refractory metal layer, the fluorinated compounds of Ti or Ta and the fluorocarbons being created during the etching step and present in the interior of the hole; and performing plasma-treatment for the interior of said hole to remove the fluorocarbon.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 29, 2007
    Applicant: NEC ELECTRONICS CORPOATION
    Inventor: Kousei Ushijima
  • Publication number: 20060214300
    Abstract: An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 28, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kenichi Yamamoto, Masashige Moritoki, Takashi Shimane, Kazumi Saito, Hiroaki Tomimori, Takamasa Itou, Kousei Ushijima, Katsuro Tateyama