Patents by Inventor Koushi Maemura

Koushi Maemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit and manufacturing method therefore
    Patent number: 6492692
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: December 10, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
  • Semiconductor dicing and assembling method
    Patent number: 6022792
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: February 8, 2000
    Assignee: Seiko Instruments, Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara