Patents by Inventor Koushi Tozuka

Koushi Tozuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and manufacturing method thereof
    Patent number: 8580652
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20110068476
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 24, 2011
    Inventors: Atsuko KAWASAKI, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue