Patents by Inventor Koushik Chakraborty

Koushik Chakraborty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130326258
    Abstract: For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation.
    Type: Application
    Filed: December 7, 2012
    Publication date: December 5, 2013
    Applicant: Utah State University
    Inventors: Sanghamitra Roy, Koushik Chakraborty
  • Patent number: 8549456
    Abstract: Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 1, 2013
    Assignee: Utah State University
    Inventors: Sanghamitra Roy, Koushik Chakraborty, Yiding Han
  • Publication number: 20130235877
    Abstract: For aging-aware routing, an aging module calculates an aging score for links and routers in a Network-on-Chip for a previous epoch. A routing module dynamically routes a flow through the links and the routers to satisfy routing criteria including a least total aging score for the links and the routers of the flow.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 12, 2013
    Applicant: UTAH STATE UNIVERSITY
    Inventors: Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
  • Publication number: 20120324250
    Abstract: For multicore power performance management, a first core has a first architecture and is designed for a first voltage-frequency domain. A second core has the first architecture and that is designed for a second voltage-frequency domain.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 20, 2012
    Applicant: UTAH STATE UNIVERSITY
    Inventors: Koushik Chakraborty, Sanghamitra Roy
  • Publication number: 20110185328
    Abstract: Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 28, 2011
    Applicant: Utah State University
    Inventors: Sanghamitra Roy, Koushik Chakraborty, Yiding Han
  • Patent number: 7962774
    Abstract: An over-provisioned multicore processor employs more cores than can simultaneously run within the power envelope of the processor, enabling advanced processor control techniques for more efficient workload execution, despite significantly decreasing the duty cycle of the active cores so that on average a full core or more may not be operating.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: June 14, 2011
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi
  • Publication number: 20090094438
    Abstract: An over-provisioned multicore processor employs more cores than can simultaneously run within the power envelope of the processor, enabling advanced processor control techniques for more efficient workload execution, despite significantly decreasing the duty cycle of the active cores so that on average a full core or more may not be operating.
    Type: Application
    Filed: October 4, 2007
    Publication date: April 9, 2009
    Inventors: Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi