Abstract: An Integrated Circuit with an automatically re-tuning analog circuit is provided. The Integrated Circuit comprises (a) an analog circuit comprising a plurality of tunable components each configured to respond to a plurality of change control bits, (b) a Process, Voltage Temperature (PVT) characteristics monitor comprising a plurality of PVT sensors, (c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory. Each tunable component is configured to change its electrical characteristics such that together each of the tunable components is enabled to retune the analog circuit to attain a predefined set of electrical characteristics.

Abstract: The present description relates to a method based on artificial intelligence to implement a wide range of microelectronic circuits that can adapt by themselves to the usage conditions (e.g. loading changes), manufacturing variances or defects (e.g. process variations, device parameter mismatches, device model inaccuracies or changes, etc.), as well as environmental conditions (e.g. voltage, temperature, interference) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions. Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals, the usage and environmental conditions.

Abstract: A system and method for synthesizing analog design in real-time using an artificial intelligence and machine learning (AI/ML) model are provided. The method includes (i) generating a behavioral model of an analog macro using the AI/ML model; (ii) determining one or more operations that is required to implement the behavioral model by scanning the behavioral model; (iii) selecting, using the AI/ML model, the analog macro based on at least one specification that corresponds to the analog macro; (iv) synthesizing, the analog macro that is selected by the AI/ML model 214 and one or more leaf cells for each selected analog macro of the behavioral architectural implementation to obtain a gate-level circuit design based on a figure of merit (FoM) of the analog macro and (v) determining, using the AI/ML model, the analog circuit design for the integrated circuit system based on the gate level circuit design that is synthesized.

Abstract: The present description relates to a method based on artificial intelligence to implement a wide range of microelectronic circuits that can adapt by themselves to the usage conditions (e.g. loading changes), manufacturing variances or defects (e.g. process variations, device parameter mismatches, device model inaccuracies or changes, etc.), as well as environmental conditions (e.g. voltage, temperature, interference) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions. Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals, the usage and environmental conditions.

Abstract: A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (“BBGEN”). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (“BBGEN”) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.

Abstract: A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (“BBGEN”). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (“BBGEN”) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.

Abstract: Temperature sensors for integrated circuits that use back-gate bias for low power operation. A temperature sensor can comprise a voltage-gate-source generator having sensing transistors; an Ibias generator; a back-gate bias generator; and a temperature read-out circuit. In a calibration mode, the temperature sensor determines a back-gate bias voltage and a resistor trimming code to be used during functional operation.

Abstract: Temperature sensors for integrated circuits that use back-gate bias for low power operation. A temperature sensor can comprise a voltage-gate-source generator having sensing transistors; an Ibias generator; a back-gate bias generator; and a temperature read-out circuit. In a calibration mode, the temperature sensor determines a back-gate bias voltage and a resistor trimming code to be used during functional operation.

Abstract: A device for controlling a power-on reset signal can include a constant current source, for controlling a reference current that is independent of a supply voltage, and a trip point detector circuit driven by the reference current. The trip point detector circuit detects when the supply voltage of the device exceeds a first trip point voltage, and de-asserts the power-on reset signal when the supply voltage exceeds the first trip point voltage. The first trip point voltage can be controlled by a sum of a threshold voltage of a first n-type metal-oxide-semiconductor transistor, a voltage drop across a first resistor, and a threshold voltage of a first p-type metal-oxide-semiconductor transistor. The device may further include a hysteresis circuit, for detecting when the supply voltage falls below a second trip point voltage and causing the trip point detector circuit to reassert the power-on reset signal.