Abstract: A contention priority control circuit which receives data of two priority classes from a plurality of input ports, and arbitrates contention between output requests for outputting these data to a bus on the basis of the priority classes and priorities determined for the respective input ports includes a plurality of arbiters which are arranged at a plurality of input ports for receiving data of the two priority classes, and receive data output requests for each of the two priority classes, a forward high-priority ring for connecting the plurality of arbiters in a forward direction, a forward low-priority ring for connecting the plurality of arbiters in the forward direction, and a backward high-priority ring for connecting the plurality of arbiters in a backward direction opposite to the forward direction.

Abstract: An output buffer type ATM (Asynchronous Transfer Mode) exchange device and a multicast control method enable retrieval processing to bit map table for the sake of multicast control to delay, and which are capable of answering to be large capacity of the bit map table. The multicast control method of the output buffer type ATM exchange device multiplexes the cell inputted from a plurality of input ports during input cell period. The method accumulates unicast cell from among the cell distributed from a time division multiple bus into output buffer corresponding to the output port respectively. The method outputs the unicast cell to corresponding output port while synchronizing with output cell period.

Abstract: Disclosed is device for suppressing a rise in the operating speed of the buffer controller in an ATM switch and reducing the operating speed in the write decision section of the switch. In a memory-write control circuit, data to be written to a memory having a predetermined memory capacity is provided with a priority. The circuit renders a write-enable/disable decision in such a manner that data of low priority will not be written to the memory in excess of a threshold value and data of high priority will not be written to the memory in excess of the memory capacity. A write decision circuit compares the threshold value and present queue length if the input data is valid data and, moreover, the data has a low priority, and compares the maximum capacity of the memory and the present queue length if the input data is valid data and, moreover, the data has a high priority, thereby to render an enable/disable decision with regard to writing of the input data to the memory.