Abstract: A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.

Abstract: A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.

Abstract: A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.

Abstract: A method, system, and computer program product are described for use with graph-based verification of a circuit design. The method comprises performing, using a graph referencing the circuit design, a predefined set of one or more test sequences. The method further comprises determining that a first coverage point of the graph is not fully hit by the predefined set, and back-traversing the graph from a second coverage point of the graph that is partially hit or fully hit by the predefined set. The method further comprises generating, based on back-traversing the graph, a prospective test sequence to fully hit the first coverage point.

Abstract: Cover points are automatically generated based on analysis of the hardware design represented in register transfer level (RTL) of a hardware description language. A cover point generator uses uncertainty of event occurrence, critical point analysis and redundancy elimination to determine consequential cover points for function verification. A user may provide input parameters to the cover point generator to define depth and width of cover events for generating cover points.

Abstract: Cover points are automatically generated based on analysis of the hardware design represented in register transfer level (RTL) of a hardware description language. A cover point generator uses uncertainty of event occurrence, critical point analysis and redundancy elimination to determine consequential cover points for function verification. A user may provide input parameters to the cover point generator to define depth and width of cover events for generating cover points.