Patents by Inventor Kousik Ganesan
Kousik Ganesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220199503Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Manish DUBEY, Guruprasad ARAKERE, Deepak KULKARNI, Sairam AGRAHARAM, Wei-Lun K. JEN, Numair AHMED, Kousik GANESAN, Amol D. JADHAV, Kyu-Oh LEE
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Patent number: 10745817Abstract: In one aspect, an apparatus includes a plating cell, a degassing device configured to remove oxygen from the plating solution prior to the plating solution flowing into the plating cell; an oxidation station configured to increase an oxidizing strength of the plating solution after the plating solution flows out of the plating cell; and a controller. The controller includes program instructions for causing a process that includes operations of: reducing an oxygen concentration of the plating solution where the plating solution contains a plating accelerator; then, contacting a wafer substrate with the plating solution having reduced oxygen concentration and electroplating a metal such that the electroplating causes a net conversion of the accelerator to a less-oxidized accelerator species within the plating cell; then increasing the oxidizing strength of the plating solution causing a net re-conversion of the less-oxidized accelerator species back to the accelerator outside the plating cell.Type: GrantFiled: October 16, 2017Date of Patent: August 18, 2020Assignee: Novellus Systems, Inc.Inventors: Kousik Ganesan, Tighe A. Spurlin, Jonathan David Reid, Shantinath Ghongadi, Andrew John McKerrow, James E. Duncan
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Publication number: 20200211952Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.Type: ApplicationFiled: March 10, 2020Publication date: July 2, 2020Inventors: Rahul N. Manepalli, Kousik Ganesan, Marcel Arlan Wall, Srinivas Pietambaram
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Patent number: 10658281Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.Type: GrantFiled: September 29, 2017Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Rahul N. Manepalli, Kousik Ganesan, Marcel Arlan Wall, Srinivas Pietambaram
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Publication number: 20200006273Abstract: A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Manish Dubey, Kousik Ganesan, Suddhasattwa Nad, Thomas Heaton, Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur
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Publication number: 20190103348Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Rahul N. Manepalli, Kousik Ganesan, Marcel Arlan Wall, Srinivas Pietambaram
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Publication number: 20180038007Abstract: In one aspect, an apparatus includes a plating cell, a degassing device configured to remove oxygen from the plating solution prior to the plating solution flowing into the plating cell; an oxidation station configured to increase an oxidizing strength of the plating solution after the plating solution flows out of the plating cell; and a controller. The controller includes program instructions for causing a process that includes operations of: reducing an oxygen concentration of the plating solution where the plating solution contains a plating accelerator; then, contacting a wafer substrate with the plating solution having reduced oxygen concentration and electroplating a metal such that the electroplating causes a net conversion of the accelerator to a less-oxidized accelerator species within the plating cell; then increasing the oxidizing strength of the plating solution causing a net re-conversion of the less-oxidized accelerator species back to the accelerator outside the plating cell.Type: ApplicationFiled: October 16, 2017Publication date: February 8, 2018Inventors: Kousik Ganesan, Tighe A. Spurlin, Jonathan David Reid, Shantinath Ghongadi, Andrew John McKerrow, James E. Duncan
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Patent number: 9816193Abstract: Methods, systems, and apparatus for plating a metal onto a work piece with a plating solution having a low oxygen concentration are described. In one aspect, a method includes reducing an oxygen concentration of a plating solution. The plating solution includes about 100 parts per million or less of an accelerator. After reducing the oxygen concentration of the plating solution, a wafer substrate is contacted with the plating solution in a plating cell. The oxygen concentration of the plating solution in the plating cell is about 1 part per million or less. A metal is electroplated with the plating solution onto the wafer substrate in the plating cell. After electroplating the metal onto the wafer substrate, an oxidizing strength of the plating solution is increased.Type: GrantFiled: December 13, 2011Date of Patent: November 14, 2017Assignee: Novellus Systems, Inc.Inventors: Kousik Ganesan, Tighe Spurlin, Jonathan D. Reid, Shantinath Ghongadi, Andrew McKerrow, James E. Duncan
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Patent number: 9685353Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.Type: GrantFiled: April 5, 2013Date of Patent: June 20, 2017Assignee: Novellus Systems, Inc.Inventors: Kousik Ganesan, Shantinath Ghongadi, Tariq Majid, Aaron Labrie, Steven T. Mayer
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Patent number: 9138784Abstract: An apparatus for conditioning deionized water and delivering it to a semiconductor wafer in a post electrofill module includes a degassing station configured to remove dissolved gas from the deionized water flow, a heating station configured to heat the deionized water flow, and a nozzle configured to deliver the deionized water flow to the wafer. The heating and degassing are performed before the delivery of the deionized water flow to the wafer. In some implementations the degassing station includes a contact degasser or an inert gas bubbler, and the heating station is configured to heating the deionized water flow to a temperature of between about 35-40° C. In some embodiments the deionized water flow is passed through the degassing station before being passed through the heating station.Type: GrantFiled: December 6, 2010Date of Patent: September 22, 2015Assignee: Novellus Systems, Inc.Inventors: Jeffrey Alan Hawkins, Charles Lorenzo Merrill, Jason Daniel Marchetti, Kousik Ganesan, Bryan L. Buckalew
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Publication number: 20140190529Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.Type: ApplicationFiled: April 5, 2013Publication date: July 10, 2014Inventors: Kousik Ganesan, Shanthinath Ghongadi, Tariq Majid, Aaron Labrie, Steven T. Mayer
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Patent number: 8540857Abstract: An apparatus for electroplating a layer of metal onto a work piece surface includes a membrane separating the chamber of the apparatus into a catholyte chamber and an anolyte chamber. In the catholyte chamber is a catholyte manifold region that includes a catholyte manifold and at least one flow distribution tube. The catholyte manifold and at least one flow distribution tube serve to mix and direct catholyte flow in the catholyte chamber. The provided configuration effectively reduces failure and improves the operational ranges of the apparatus.Type: GrantFiled: August 9, 2012Date of Patent: September 24, 2013Assignee: Novellus Systems, Inc.Inventors: Steven Mayer, Shantinath Ghongadi, Kousik Ganesan, Zhian He, Jingbin Feng
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Patent number: 8419964Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.Type: GrantFiled: August 27, 2008Date of Patent: April 16, 2013Assignee: Novellus Systems, Inc.Inventors: Kousik Ganesan, Shanthinath Ghongadi, Tariq Majid, Aaron Labrie, Steven T. Mayer
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Patent number: 8398831Abstract: Embodiments of a closed-contact electroplating cup assembly that may be rapidly cleaned while an electroplating system is on-line are disclosed. One disclosed embodiment comprises a cup assembly and a cone assembly, wherein the cup assembly comprises a cup bottom comprising an opening, a seal surrounding the opening, an electrical contact structure comprising a plurality of electrical contacts disposed around the opening, and an interior cup side that is tapered inwardly in along an axial direction of the cup from a cup top toward the cup bottom.Type: GrantFiled: April 4, 2011Date of Patent: March 19, 2013Assignee: Novellus Systems, Inc.Inventors: Shantinath Ghongadi, Robert Rash, Jeff Hawkins, Seshasayee Varadarajan, Tariq Majid, Kousik Ganesan, Bryan Buckalew, Brian Evans
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Patent number: 8377268Abstract: Embodiments of a closed-contact electroplating cup are disclosed. One embodiment comprises a cup bottom comprising an opening, and a seal disposed on the cup bottom around the opening. The seal comprises a wafer-contacting peak located substantially at an inner edge of the seal. The embodiment also comprises an electrical contact structure disposed over a portion of the seal, wherein the electrical contact structure comprises an outer ring and a plurality of contacts extending inwardly from the outer ring, and wherein each contact has a generally flat wafer-contacting surface. The embodiment further comprises a wafer-centering mechanism configured to center a wafer in the cup.Type: GrantFiled: June 6, 2011Date of Patent: February 19, 2013Assignee: Novellus Systems, Inc.Inventors: Robert Rash, Shantinath Ghongadi, Kousik Ganesan, Zhian He, Tariq Majid, Jeff Hawkins, Seshasayee Varadarajan, Bryan Buckalew
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Patent number: 8262871Abstract: An apparatus for electroplating a layer of metal onto a work piece surface includes a membrane separating the chamber of the apparatus into a catholyte chamber and an anolyte chamber. In the catholyte chamber is a catholyte manifold region that includes a catholyte manifold and at least one flow distribution tube. The catholyte manifold and at least one flow distribution tube serve to mix and direct catholyte flow in the catholyte chamber. The provided configuration effectively reduces failure and improves the operational ranges of the apparatus.Type: GrantFiled: December 17, 2009Date of Patent: September 11, 2012Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Shantinath Ghongadi, Kousik Ganesan, Zhian He, Jingbin Feng
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Publication number: 20120181170Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.Type: ApplicationFiled: March 28, 2012Publication date: July 19, 2012Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida
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Publication number: 20120175263Abstract: Methods, systems, and apparatus for plating a metal onto a work piece with a plating solution having a low oxygen concentration are described. In one aspect, a method includes reducing an oxygen concentration of a plating solution. The plating solution includes about 100 parts per million or less of an accelerator. After reducing the oxygen concentration of the plating solution, a wafer substrate is contacted with the plating solution in a plating cell. The oxygen concentration of the plating solution in the plating cell is about 1 part per million or less. A metal is electroplated with the plating solution onto the wafer substrate in the plating cell. After electroplating the metal onto the wafer substrate, an oxidizing strength of the plating solution is increased.Type: ApplicationFiled: December 13, 2011Publication date: July 12, 2012Inventors: Kousik GANESAN, Tighe SPURLIN, Jonathan D. REID, Shantinath GHONGADI, Andrew McKERROW, James E. DUNCAN
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Patent number: 8172992Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.Type: GrantFiled: December 8, 2009Date of Patent: May 8, 2012Assignee: Novellus Systems, Inc.Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida
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Patent number: 8172646Abstract: Provided are magnetically actuated wafer chucks that permit a wafer to be clamped or unclamped at any time during a process and at any rotational speed, as desired. Such wafer chucks may include constraining members that are movable between open and closed positions. In a closed position, a constraining member aligns the wafer after wafer handoff and/or clamps the wafer during rotation to prevent it from flying off the chuck. In an open position, the constraining member moves away from the wafer to allow liquid etchant to flow from the wafer edge without obstruction. The constraining members may be, for example, cams, attached to arms or links of the chuck. The cams or other constraining members move between open and closed positions by self-balancing forces including a first force, such as a spring force, that acts to move a cam in a first direction, and a non-contact actuate-able force, such as a magnetic force, that acts to move the cam in the opposite direction.Type: GrantFiled: February 27, 2009Date of Patent: May 8, 2012Assignee: Novellus Systems, Inc.Inventors: Jingbin Feng, Aaron LaBrie, Kousik Ganesan