Patents by Inventor Kousuke Okuyama
Kousuke Okuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20020006054Abstract: An information retention capability based on a memory cell which comprises a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.Type: ApplicationFiled: August 31, 2001Publication date: January 17, 2002Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
-
Publication number: 20010025963Abstract: Disclosed herein is a semiconductor device wherein a thyristor protective element and a trigger element are provided in a semiconductor layer formed on a buried insulating layer, and a trigger electrode (gate) of the thyristor protective element and a back gate of the trigger element are provided in the same p well and electrically connected to each other to thereby drive the thyristor protective element based on a substrate current produced by the breakdown of the trigger element.Type: ApplicationFiled: March 13, 2001Publication date: October 4, 2001Inventors: Yoshiyasu Tashiro, Nobuhiro Kasa, Kousuke Okuyama, Hiroyasu Ishizuka
-
Patent number: 5880497Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.Type: GrantFiled: January 26, 1996Date of Patent: March 9, 1999Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto
-
Patent number: 5610089Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.Type: GrantFiled: April 27, 1995Date of Patent: March 11, 1997Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
-
Patent number: 5534723Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region.Type: GrantFiled: April 27, 1995Date of Patent: July 9, 1996Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
-
Patent number: 5508540Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.Type: GrantFiled: February 2, 1994Date of Patent: April 16, 1996Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto
-
Patent number: 5436484Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.Type: GrantFiled: October 29, 1993Date of Patent: July 25, 1995Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
-
Patent number: 5436483Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.Type: GrantFiled: October 29, 1993Date of Patent: July 25, 1995Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
-
Patent number: 5276346Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.Type: GrantFiled: January 2, 1992Date of Patent: January 4, 1994Assignee: Hitachi, Ltd.Inventors: Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Kazuyuki Miyazawa, Hisao Katto, Kousuke Okuyama
-
Patent number: 5063170Abstract: A semiconductor integrated circuit device having a read-only memory which comprises a plurality of first gate electrodes arranged on a semiconductor substrate in a first direction maintaining a predetermined distance, a plurality of second gate electrodes that are arranged among said first gate electrodes and are partly overlapped on said first gate electrodes, and regions of data-writing impurities positioned under the first and second gate electrodes. The impurities for writing data are introduced through the first or second gate electrodes using the overlappings of the first and second gate electrodes as masks.Type: GrantFiled: January 2, 1990Date of Patent: November 5, 1991Assignee: Hitachi, Ltd.Inventor: Kousuke Okuyama
-
Patent number: 4904615Abstract: Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Type: GrantFiled: January 26, 1989Date of Patent: February 27, 1990Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Kousuke Okuyama, Ken Uchida, Kouichi Kusuyama, Satoshi Meguro, Hisao Katto, Kazuhiro Komori
-
Patent number: 4898840Abstract: A semiconductor integrated circuit device having a read-only memory which comprises a plurality of first gate electrodes arranged on a semiconductor substrate in a first direction maintaining a predetermined distance, a plurality of second gate electrodes that are arranged among said first gate electrodes and are partly overlapped on said first gate electrodes, and regions of data-writing impurities positioned under the first and second gate electrodes. The impurities for writing data are introduced through the first or second gate electrodes using the overlappings of the first and second gate electrodes as masks.Type: GrantFiled: November 10, 1988Date of Patent: February 6, 1990Assignee: Hitachi, Ltd.Inventor: Kousuke Okuyama
-
Patent number: 4818716Abstract: Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Type: GrantFiled: October 22, 1987Date of Patent: April 4, 1989Assignees: Hitachi Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Kousuke Okuyama, Ken Uchida, Kouichi Kusuyama, Satoshi Meguro, Hisao Katto, Kazuhiro Komori
-
Patent number: 4784968Abstract: Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.Type: GrantFiled: July 20, 1987Date of Patent: November 15, 1988Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, Kousuke Okuyama
-
Patent number: 4717684Abstract: A semiconductor integrated circuit device wherein the source and drain regions of a MOSFET in an internal circuit have lightly doped drain (LDD) structures in order to suppress the appearance of hot carriers, and the source and drain regions of a MOSFET in an input/output circuit have structures doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.Type: GrantFiled: February 3, 1986Date of Patent: January 5, 1988Assignee: Hitachi, Ltd.Inventors: Hisao Katto, Kousuke Okuyama
-
Patent number: 4697198Abstract: Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.Type: GrantFiled: August 8, 1985Date of Patent: September 29, 1987Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, Kousuke Okuyama
-
Patent number: 4652897Abstract: A semiconductor memory device wherein a portion of source region of a field-effect transistor that serves as a memory cell has a low impurity concentration, so that hot carriers generated on the source side are injected into the floating gate. Hot carriers are generated by utilizing a large electric field intensity established by the drop of voltage in the region of low impurity concentration. The voltage difference is so great between the source region and the control gate that hot carriers generated on the source side are efficiently injected into the floating gate.Type: GrantFiled: July 15, 1985Date of Patent: March 24, 1987Assignee: Hitachi, Ltd.Inventors: Kousuke Okuyama, Kazuhiro Komori, Hisao Katto
-
Patent number: 4637124Abstract: Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.Type: GrantFiled: March 18, 1985Date of Patent: January 20, 1987Assignee: Hitachi, Ltd.Inventors: Kousuke Okuyama, Norio Suzuki, Satoshi Meguro, Kouichi Nagasawa