Patents by Inventor Kousuke Yoshida

Kousuke Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250225208
    Abstract: A mobile driver's license issuing apparatus comprising: confirming unit that combis, based on combination information set in advance, first biometric information of an applicant that has been stored in advance in a driver's license information storage device connected to a dedicated line, second biometric information acquired by real-time image capture of the applicant, and third biometric information of the applicant held by an integrated circuit (IC)-based driver's license owned by the applicant, and for executing an identity verification process on each combination; and issuing unit that issues, when identity verification has succeeded, mobile driver's license information, which has been generated based on driver's license information of the applicant acquired from the driver's license information storage device, to a terminal owned by the applicant so as to store the mobile driver's license information in a storage area of the terminal.
    Type: Application
    Filed: March 10, 2022
    Publication date: July 10, 2025
    Applicant: NEC Corporation
    Inventors: Nobuhisa Takahashi, Kousuke Yoshida, Hiroshi Fukuda, Yoshinori Saida
  • Publication number: 20220190568
    Abstract: It is aimed to provide a flexible exterior member for wire guide 12 including a hollow tubular portion 34 to be sheathed on a wire guide 10 bendable and deformable into a predetermined shape, a slit 36 provided over an entire length in an axial direction of the tubular portion 34, and a pair of joining portions 48, 48 respectively provided on a pair of circumferential end surfaces 50, 50 of the tubular portion 34 divided by the slit 36, the pair of joining portions 48, 48 being put together and joined to each other, and a wire guide device G using this flexible exterior member for wire guide 12.
    Type: Application
    Filed: December 27, 2019
    Publication date: June 16, 2022
    Inventors: Kousuke YOSHIDA, Hiroki UNO, Hiroshi INOUE
  • Patent number: 10746152
    Abstract: In an ignition device, a proportion of a yoke end width defined as a distance from one end to another end of an end portion of each of a pair of yokes in the circumferential direction to a magnet width defined as a distance from one end to another end of a permanent magnet disposed on the outer circumferential surface of a flywheel, in the circumferential direction is in a range of 60% to 100%. Moreover, a proportion of the magnet width to a yoke interval between the pair of yokes is in a range of 95% to 100%.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: August 18, 2020
    Assignee: TOYO DENSO CO., LTD.
    Inventors: Takeshi Oana, Kousuke Yoshida
  • Publication number: 20190390642
    Abstract: In an ignition device, a proportion of a yoke end width defined as a distance from one end to another end of an end portion of each of a pair of yokes in the circumferential direction to a magnet width defined as a distance from one end to another end of a permanent magnet disposed on the outer circumferential surface of a flywheel, in the circumferential direction is in a range of 60% to 100%. Moreover, a proportion of the magnet width to a yoke interval between the pair of yokes is in a range of 95% to 100%.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Applicant: Toyo Denso Co., Ltd.
    Inventors: Takeshi OANA, Kousuke YOSHIDA
  • Patent number: 8536680
    Abstract: An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yukio Takahashi, Kousuke Yoshida
  • Patent number: 8445801
    Abstract: A switch comprises a room light case, a switch knob arranged inside an aperture portion of the room light case, guide grooves provided on an inner circumferential face of the aperture portion of the room light case, and guide ribs provided on an outer circumferential face of the switch knob. The switch knob moves for a switch stroke part in a depth direction of the aperture portion, from a waiting position to a pressed-down position by a pressing down operation. The guide grooves are provided in a range deeper than a depth size of the switch stroke from an opening edge located on the switch case surface side of the aperture portion.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: May 21, 2013
    Assignee: Yazaki Corporation
    Inventor: Kousuke Yoshida
  • Publication number: 20100244129
    Abstract: Second-conductivity-type high dose impurity layers are formed in a device forming region, and function as the source and drain; a second-conductivity-type low dose impurity layer is provided around each of the second-conductivity-type high dose impurity layers so as to expand each second-conductivity-type high dose impurity layer in the depth-wise direction and in the direction of channel length, at least a part of the second-conductivity-type low dose impurity layer is positioned below the gate electrode, and the gate insulting film; and the gate insulating film has, at a portion thereof positioned above the second-conductivity-type low dose impurity layer, a sloped portion which continuously increases in the thickness from the center towards a side face of the gate electrode, without causing an inflection point.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 30, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Kousuke Yoshida
  • Publication number: 20090302423
    Abstract: An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 10, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yukio Takahashi, Kousuke Yoshida
  • Publication number: 20090242984
    Abstract: Aimed at providing a semiconductor device capable preventing transistor characteristics from departing from design characteristics, the semiconductor device of the present invention has a gate insulating film and a gate electrode positioned over a channel forming region; two second-conductivity-type, high-concentration impurity diffused layers which function as the source and drain of a transistor; two second-conductivity-type, low-concentration impurity diffused layers having a concentration lower than that of the second-conductivity-type, high-concentration impurity diffused layers, provided respectively around the second-conductivity-type, high-concentration impurity diffused layers, so as to expand the second-conductivity-type, high-concentration impurity diffused layers in the depth-wise direction and the channel-length-wise direction; and a first-conductivity-type buried layer having a concentration higher than that of the semiconductor layer, positioned below the second-conductivity-type, low-concentra
    Type: Application
    Filed: February 24, 2009
    Publication date: October 1, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kousuke Yoshida
  • Publication number: 20080173525
    Abstract: A switch comprises a room light case, a switch knob arranged inside an aperture portion of the room light case, guide grooves provided on an inner circumferential face of the aperture portion of the room light case, and guide ribs provided on an outer circumferential face of the switch knob. The switch knob moves for a switch stroke part in a depth direction of the aperture portion, from a waiting position to a pressed-down position by a pressing down operation. The guide grooves are provided in a range deeper than a depth size of the switch stroke from an opening edge located on the switch case surface side of the aperture portion.
    Type: Application
    Filed: January 18, 2008
    Publication date: July 24, 2008
    Inventor: Kousuke YOSHIDA
  • Patent number: 6476641
    Abstract: A low power consuming circuit is provided which is capable of reducing power consumption by using a Vt (threshold voltage) characteristic of a MIS (Metal Insulator Semiconductor) transistor for generating a source voltage. N-channel transistors making up an inverter is configured by being stacked vertically. An N-channel transistor source voltage control circuit controls voltages so that a gate voltage of an N-channel transistor source voltage bias transistor existing in a lower state is transferred to a drain voltage terminal of the N-channel transistor source voltage bias transistor or to a supply voltage terminal.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: November 5, 2002
    Assignee: NEC Corporation
    Inventor: Kousuke Yoshida
  • Publication number: 20010050379
    Abstract: A low power consuming circuit is provided which is capable of reducing power consumption by using a Vt (threshold voltage) characteristic of a MIS (Metal Insulator Semiconductor) transistor for generating a source voltage.
    Type: Application
    Filed: July 3, 2001
    Publication date: December 13, 2001
    Applicant: NEC Corporation
    Inventor: Kousuke Yoshida
  • Patent number: 5990731
    Abstract: Input/output circuitry for electrically protecting an internal element includes an input/output terminal connected to the internal element, a pair of first and second power terminals applied with a bias voltage, a series connection of a diode and a bipolar transistor between the pair of first and second power terminals so that an intermediate point between the diode and the bipolar transistor is connected to the input terminal, and a parasitic resistance connected between a base of the bipolar transistor and the diode so that the diode is connected between the parasitic resistance and an emitter of the bipolar transistor. An electrostatic pulse applied to the input/output terminal is clamped by the series connection of the diode and the bipolar transistor to protect the internal element from an electrostatic pulse applied to the input/output terminal.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: November 23, 1999
    Assignee: NEC Corporation
    Inventor: Kousuke Yoshida
  • Patent number: 5747354
    Abstract: The invention provides an n-channel MOS field effect transistor with an anti-radioactivity. The transistor includes leak guard boron diffusion layers, each of which has a junction surface to an isolation oxide film. The junction surface exists up to a deeper level than a predetermined depth corresponding to a junction surface of n-type source and drain diffusion layers and a p-type silicon substrate. Such leak guard boron diffusion layer is formed by ion-implantation of boron through a gate oxide film, after a formation of the gate oxide film. Such leak guard boron diffusion layers have a higher impurity concentration. The existence of the leak guard boron diffusion layers suppresses a leak to be generated by radiation damages of silicon oxide film such as the gate oxide film and the isolation oxide film.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: May 5, 1998
    Assignee: NEC Corporation
    Inventor: Kousuke Yoshida
  • Patent number: 5723886
    Abstract: The invention provides an n-channel MOS field effect transistor with an improved anti-radioactivity. Such transistor includes a p-type silicon substrate. An isolation oxide film is selectively formed on a surface of the p-type silicon substrate. Source and drain diffusion layers of n+-type are formed on first opposite sides of a channel region in the p-type silicon substrate. A gate made of polycrystalline silicon is formed over the channel region through a gate oxide film. Leak guard diffusion layers of p-type are formed on second opposite sides of the channel region in the p-type silicon substrate. The p-type leak guard diffusion layer has a junction surface to the isolation oxide film. The junction surface of the p-type leak guard diffusion layer and the isolation oxide film exists up to a level which is deeper than a depth of the n+-type source and drain diffusion layers.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: March 3, 1998
    Assignee: NEC Corporation
    Inventor: Kousuke Yoshida
  • Patent number: 5160708
    Abstract: The invention relates to a dry type simultaneous desulfurization and dedusting method in forming moving beds with a granulate desulfurizing and dedusting agent containing as the principle composition 5-95 weight % of iron oxide and 95-5 weight % of metallic iron, and contacting these moving beds with the gas containing hydrogen sulfide and dust, thereby simultaneously desulfurizing and dedusting the gas.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: November 3, 1992
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Kenzaburo Kodama, Kenji Kamei, Kousuke Yoshida, Katsuya Ishikawa, Yukio Kubo, Yoshiaki Takatani
  • Patent number: 5102636
    Abstract: A dry type simultaneous desulfurization and dedusting method directed to forming moving beds with granulate desulfurizing and dedusting agent containing as the principle composition 5-95 weight % of iron oxide and 95-5 weight % of metallic iron, and contacting these moving beds with the gas containing hydrogen sulfide and dust, thereby simultaneously desulfurizing and dedusting the gas.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: April 7, 1992
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Kenzaburo Kodama, Kenji Kamei, Kousuke Yoshida, Katsuya Ishikawa, Yukio Kubo, Takatani Yoshiaki