Patents by Inventor Kouta Soejima

Kouta Soejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080205646
    Abstract: A method, device and computer-readable recording medium that stores therein a computer program for data decryption to execute processing when encrypted communication data including encrypted data obtained by encrypting plain text data and communication attributive data representing information of a data size of communicated data is received, the computer program making a computer execute notifying for receiving only the communication attributive data in the encrypted communication data and notifying the data size represented by the received communication attributive data to a preparing unit which prepares a storage area for storing the encrypted communication data in temporary storage incorporated in the computer. The computer program also enables the computer to execute storing the encrypted communication data in the prepared storage area and decrypting the encrypted data contained in the encrypted communication data, which is stored in the storage area, to obtain the plain text data.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 28, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyuki KOMORI, Jun Yajima, Tetsuhiro Kodama, Kouta Soejima
  • Patent number: 6028473
    Abstract: A charge pump apparatus which comprises first and second active capacitors in series, having a common node between them. The second node of the second active capacitor is coupled to a particular node in the charge pump which drives an output of the charge pump. A pump clock is connect to the first lead of the first active capacitor. A voltage clamp is connected to the particular node and provides a bias point. A dynamic biasing circuit is connected to the common node and charges the common node and the particular node during intervals between transitions of the pump clock to keep both the first and second active capacitors activated during the transitions of the pump clock.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: February 22, 2000
    Assignee: Macronix International Co., Ltd.
    Inventors: Teruhiko Kamei, Kouta Soejima, I-Long Lee, Ray-Lin Wan
  • Patent number: 5644534
    Abstract: A booster circuit is provided with first and second booster circuit sections, which have the same construction and each of which is provided with capacitors and transistors for controlling the gate voltage of each of the final stage output transistor. The output terminals of the first and second booster circuit sections are connected to each other. Input pulses F1 to F4 are inputted to positions of first and second booster circuit sections, respectively. Input positions of F2 are replaced with those of F4 between the first and second raising circuit sections. Likewise, input positions of F1 are replaced with those of F3 therebetween. As a result, the first and second booster circuit sections operate, while having phases opposite each other. The booster circuit thus provides less voltage loss, smoother output voltage and a higher voltage raising capability.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: July 1, 1997
    Assignee: Macronix International Co., Ltd.
    Inventor: Kouta Soejima