Patents by Inventor Kouta Takahashi

Kouta Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949005
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 8227323
    Abstract: A method for manufacturing a semiconductor device is disclosed in which, after semiconductor function regions and patterns of interlayer insulating films including required contact holes are formed on one main surface side of a semiconductor substrate, an aluminum film or an aluminum alloy film which is thick is formed all over the main surface side of the semiconductor substrate and brought into conductive contact with the surface of the semiconductor substrate including bottom surfaces of the contact holes so as to form a required electrode film. Formation of the aluminum film or the aluminum alloy film is divided into a plurality of steps so that the thickness of the aluminum film or the aluminum alloy film is formed gradually, and between every two of the plurality of steps of forming the aluminum film or the aluminum alloy film, there is provided a step of performing isotropic etching to flatten irregularities in a surface of the aluminum film or the aluminum alloy film formed in the previous step.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: July 24, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kouta Takahashi, Takeshi Fujii
  • Patent number: 8138542
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: March 20, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
  • Patent number: 7888243
    Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: February 15, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Kouta Takahashi, Susumu Iwamoto
  • Publication number: 20100323499
    Abstract: A method for manufacturing a semiconductor device is disclosed in which, after semiconductor function regions and patterns of interlayer insulating films including required contact holes are formed on one main surface side of a semiconductor substrate, an aluminum film or an aluminum alloy film which is thick is formed all over the main surface side of the semiconductor substrate and brought into conductive contact with the surface of the semiconductor substrate including bottom surfaces of the contact holes so as to form a required electrode film. Formation of the aluminum film or the aluminum alloy film is divided into a plurality of steps so that the thickness of the aluminum film or the aluminum alloy film is formed gradually, and between every two of the plurality of steps of forming the aluminum film or the aluminum alloy film, there is provided a step of performing isotropic etching to flatten irregularities in a surface of the aluminum film or the aluminum alloy film formed in the previous step.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 23, 2010
    Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.
    Inventors: Kouta Takahashi, Takeshi Fujii
  • Publication number: 20100022075
    Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 28, 2010
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Kouta TAKAHASHI, Susumu IWAMOTO
  • Patent number: 7605061
    Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: October 20, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Kouta Takahashi, Susumu Iwamoto
  • Publication number: 20090206398
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Application
    Filed: April 21, 2009
    Publication date: August 20, 2009
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Koh YOSHIKAWA, Akio SUGI, Kouta TAKAHASHI, Manabu TAKEI, Haruo NAKAZAWA, Noriyuki IWAMURO
  • Patent number: 7535059
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: May 19, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
  • Publication number: 20070207597
    Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
    Type: Application
    Filed: May 8, 2007
    Publication date: September 6, 2007
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Kouta Takahashi, Susumu Iwamoto
  • Patent number: 7262459
    Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: August 28, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Kouta Takahashi, Susumu Iwamoto
  • Publication number: 20070158740
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Application
    Filed: November 28, 2006
    Publication date: July 12, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
  • Publication number: 20050184336
    Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 25, 2005
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Kouta Takahashi, Susumu Iwamoto