Patents by Inventor Koutaro Machidera

Koutaro Machidera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Control unit for activating an occupant protection means in a motor vehicle and method for monitoring the proper functioning of a control unit preferably of this type
    Patent number: 7426430
    Abstract: The invention relates to a control unit for activating an occupant protection means in a motor vehicle and to a method for monitoring the proper functioning of a control unit preferably of this type. To this end, the control unit comprises a first and a second arithmetic unit (R1, R2) as well as an activating unit (AE). A number of logical AND gates (AND1, AND2; AND3) are connected on the input side to the clock signals (clk1, clk2, clk3) of the arithmetic units (R1, R2) respectively assigned thereto or to the activating unit (AE). The signal output of each logical AND gate (AND1, AND2; AND3) is fed to a respectively assigned pulse count comparator unit (PZVE1, PZVE2) whose respective signal output is, in turn, connected to an input of a respectively assigned resetter (RES1, RES2).
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: September 16, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventors: Helge Graβhoff, Koutaro Machidera
  • Control unit for activating an occupant protection means in a motor vehicle and method for monitoring the proper functioning of a control unit preferably of this type
    Publication number: 20060064217
    Abstract: The invention relates to a control unit for activating an occupant protection means in a motor vehicle and to a method for monitoring the proper functioning of a control unit preferably of this type. To this end, the control unit comprises a first and a second arithmetic unit (R1, R2) as well as an activating unit (AE). A number of logical AND gates (AND1, AND2; AND3) are connected on the input side to the clock signals (clk1, clk2, clk3) of the arithmetic units (R1, R2) respectively assigned thereto or to the activating unit (AE). The signal output of each logical AND gate (AND1, AND2; AND3) is fed to a respectively assigned pulse count comparator unit (PZVE1, PZVE2) whose respective signal output is, in turn, connected to an input of a respectively assigned resetter (RES1, RES2).
    Type: Application
    Filed: November 12, 2003
    Publication date: March 23, 2006
    Inventors: Helge Grasshoff, Koutaro Machidera