Abstract: [Problem] To provide a microprocessor in which the bottleneck due to data sharing during memory access when a CPU and a plurality of accelerators are operated in a linked up manner can be minimized, whereby enhanced multimedia processing performance can be achieved. [Means for solving the problem] A multimedia microprocessor 1 includes a CPU 11 and accelerators 12 in which the CPU 11 and the accelerators 12 perform multimedia processing in a linked up manner. In order to prevent the bottleneck caused by data sharing during memory access between the CPU 11 and the accelerators 12 via a memory 2, an I/O dedicated cache 14 is provided in front of the memory 2 to which the CPU 11 and the accelerators 12 can commonly access. Data required for data sharing is stored in the I/O dedicated cache 14, whereby data sharing between the CPU 11 and the accelerators 12 can be performed at higher speed and the speed of multimedia processing can be increased.