Patents by Inventor Koutarou Sho

Koutarou Sho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10068915
    Abstract: According to one embodiment, a semiconductor device includes a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate and openings different in depth surrounded by the stacked body and separated from each other.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagai, Eiji Yoneda, Kentaro Matsunaga, Koutarou Sho
  • Patent number: 9972547
    Abstract: According to one embodiment, there is provided a measurement method. The method includes measuring an amount of overlay shift between a first layer and a second layer using a first overlay mark and a second overlay mark. The first layer is provided as a layer including the first overlay mark above a first substrate. The second layer is provided as a layer including the second overlay mark above the first overlay mark. The method includes acquiring a parameter related to asymmetry of a shape of the second overlay mark. The method includes obtaining an amount of correction with respect to a measured value of the amount of overlay shift based on the acquired parameter and the measured amount of overlay shift.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 15, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koutarou Sho
  • Publication number: 20170263508
    Abstract: According to one embodiment, there is provided a measurement method. The method includes measuring an amount of overlay shift between a first layer and a second layer using a first overlay mark and a second overlay mark. The first layer is provided as a layer including the first overlay mark above a first substrate. The second layer is provided as a layer including the second overlay mark above the first overlay mark. The method includes acquiring a parameter related to asymmetry of a shape of the second overlay mark. The method includes obtaining an amount of correction with respect to a measured value of the amount of overlay shift based on the acquired parameter and the measured amount of overlay shift.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Koutarou SHO
  • Publication number: 20170092656
    Abstract: According to one embodiment, a semiconductor device includes a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate and openings different in depth surrounded by the stacked body and separated from each other.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGAI, Eiji Yoneda, Kentaro Matsunaga, Koutarou Sho
  • Publication number: 20160260731
    Abstract: According to one embodiment, a semiconductor device includes a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate and openings different in depth surrounded by the stacked body and separated from each other.
    Type: Application
    Filed: June 24, 2015
    Publication date: September 8, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGAI, Eiji YONEDA, Kentaro MATSUNAGA, Koutarou SHO
  • Publication number: 20160071763
    Abstract: According to one embodiment, at first, while a resist pattern is used as a mask, a first set of one of the first layers and one of the second layers, which is an uppermost set in a stacked body and is exposed, is etched. Then, a hardening layer having a predetermined thickness is formed on an upper side of the resist pattern. Thereafter, slimming is performed to the resist pattern in its in-plane direction perpendicular to its thickness direction. The slimming is completed after the hardening layer is entirely removed or at the same time when the hardening layer is entirely removed. Then, while the resist pattern is used as a mask, a set of one of the first layers and one of the second layers is etched at an exposed area of the stacked body.
    Type: Application
    Filed: January 7, 2015
    Publication date: March 10, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Koutarou SHO
  • Publication number: 20150220846
    Abstract: According to one embodiment, a process conversion difference in a processed pattern having undergone a process via the resist pattern can be predicted, based on results of simulation of a cross-sectional shape of the resist pattern by which predicted values of resist dimensions adapted to a relationship between a parameter for lithography and actual measurement values of the resist dimensions.
    Type: Application
    Filed: May 28, 2014
    Publication date: August 6, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ai INOUE, Minoru Inomoto, Kazuyuki Masukawa, Koutarou Sho, Seiro Miyoshi, Satoshi Usui
  • Publication number: 20140232998
    Abstract: A semiconductor manufacturing apparatus according to the present embodiment comprises a vacuum chamber. A first stage is configured to temporarily attach a reticle thereonto in order to attract a foreign material present on a back surface of the reticle. A second stage is configured to attach the reticle thereonto after attaching the reticle onto the first stage in order to expose a semiconductor substrate to light using the reticle within the vacuum chamber. An exposure unit is configured to expose a surface of the semiconductor substrate to the light using the reticle attached onto the second stage.
    Type: Application
    Filed: September 6, 2013
    Publication date: August 21, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Koutarou SHO
  • Patent number: 8119313
    Abstract: A method for manufacturing a semiconductor device, includes: supplying a liquid resist containing a water-repellent additive to a surface of a rotating semiconductor wafer fixed to a rotary support to form a resist film to a design thickness on the surface of the semiconductor wafer; spin drying the resist film; bringing a liquid into contact with the resist film and exposing the resist film through the liquid after the spin drying; developing the resist film to form a resist pattern; and performing processing on the semiconductor wafer. A condition for adjusting contact angle between the resist film surface and the liquid is controlled so that the contact angle assumes a desired value, the condition including at least one selected from the group consisting of spin drying time for the resist film, resist temperature during the supplying, pressure of an atmosphere above the semiconductor wafer surface, and humidity of the atmosphere above the semiconductor wafer surface.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsutoshi Kobayashi, Daizo Muto, Koutarou Sho, Tsukasa Azuma
  • Publication number: 20100227262
    Abstract: A method for manufacturing a semiconductor device, includes: supplying a liquid resist containing a water-repellent additive to a surface of a rotating semiconductor wafer fixed to a rotary support to form a resist film to a design thickness on the surface of the semiconductor wafer; spin drying the resist film; bringing a liquid into contact with the resist film and exposing the resist film through the liquid after the spin drying; developing the resist film to form a resist pattern; and performing processing on the semiconductor wafer. A condition for adjusting contact angle between the resist film surface and the liquid is controlled so that the contact angle assumes a desired value, the condition including at least one selected from the group consisting of spin drying time for the resist film, resist temperature during the supplying, pressure of an atmosphere above the semiconductor wafer surface, and humidity of the atmosphere above the semiconductor wafer surface.
    Type: Application
    Filed: January 29, 2010
    Publication date: September 9, 2010
    Inventors: Katsutoshi KOBAYASHI, Daizo Muto, Koutarou Sho, Tsukasa Azuma
  • Publication number: 20100119982
    Abstract: An etching method according to an embodiment includes forming a resist film on a workpiece film, exposing the resist film, developing the resist film so as to form a resist pattern, selectively irradiating a particular place of the resist pattern with an energy beam so as to generate an acid component in the particular place of the resist pattern, forming a film including a cross-linking agent that causes a cross-linking reaction due to the acid component on the workpiece film so as to cover the particular place of the resist pattern where the acid component is generated, reacting the cross-linking agent with the resist pattern so as to form a cross-linked layer in a part of the resist pattern and processing the workpiece film by using the resist pattern and the cross-linked layer as a mask.
    Type: Application
    Filed: September 14, 2009
    Publication date: May 13, 2010
    Inventor: Koutarou SHO
  • Patent number: 7683291
    Abstract: According to an aspect of the invention, there is provided a single substrate processing method which continuously heats substrates to be processed to which films containing solvents are applied, by use of a heating apparatus having an opening/closing mechanism, including supplying a gas containing a solvent contained in a film of a first substrate to be processed into the heating apparatus in a closed state of the opening/closing mechanism between processing of the first substrate to be processed and processing of a second substrate to be processed.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: March 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Tsuyoshi Shibata, Koutarou Sho, Shinichi Ito
  • Patent number: 7662542
    Abstract: A pattern forming method includes the following steps. A resist pattern is formed on a to-be-processed film. A mask pattern including the resist pattern and a resin film formed on a surface of the resist pattern is formed. Slimming of the mask pattern is executed.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: February 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Shiobara, Takehiro Kondoh, Yuji Kobayashi, Koutarou Sho
  • Publication number: 20060289431
    Abstract: According to an aspect of the invention, there is provided a single substrate processing method which continuously heats substrates to be processed to which films containing solvents are applied, by use of a heating apparatus having an opening/closing mechanism, including supplying a gas containing a solvent contained in a film of a first substrate to be processed into the heating apparatus in a closed state of the opening/closing mechanism between processing of the first substrate to be processed and processing of a second substrate to be processed.
    Type: Application
    Filed: April 26, 2006
    Publication date: December 28, 2006
    Inventors: Kei Hayasaki, Tsuyoshi Shibata, Koutarou Sho, Shinichi Ito
  • Publication number: 20060189147
    Abstract: A pattern forming method includes the following teps. A resist pattern is formed on a to-be-processed film. A mask pattern including the resist pattern and a resin film formed on a surface of the resist pattern is formed. Slimming of the mask pattern is executed.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 24, 2006
    Inventors: Eishi Shiobara, Takehiro Kondoh, Yuji Kobayashi, Koutarou Sho
  • Patent number: 6162745
    Abstract: A film forming method includes the steps of forming a solution film, by dropwise supplying a solution containing solid contents in a solvent and volatilizing the solvent, and selectively forming a film of the solid contents on a to-be-processed substrate at predetermined areas, the method comprising the steps of selectively irradiating an energy beam onto that substrate surface to allow the substrate surface to be modified and forming a filmed area having a high affinity for the solvent and a non-filmed area having a low affinity for the solvent, dropwise supplying the solution to the substrate surface and forming the solution film, and volatilizing the solvent from the solution film and, by doing so, forming a solid contents film selectively on the substrate surface selectively at filmed areas.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: December 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Katsuya Okumura, Koutarou Sho