Patents by Inventor Kouzou Kage

Kouzou Kage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4301539
    Abstract: A phase shift monitoring system is provided for a mobile communication system which includes a central, or base station, one or more sub-base stations, and a plurality of mobile units. Each sub-base station is provided with a detection means which is operable to transmit an alarm signal to the base station when a predetermined tolerable phase shift is exceeded. The base station includes means for readjusting the transmission timing in order to compensate for the detected phase shift, either automatically or by manual control.
    Type: Grant
    Filed: March 10, 1980
    Date of Patent: November 17, 1981
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Kouzou Kage
  • Patent number: 4288751
    Abstract: A wave translating circuit includes a capacitor supplied with an input signal, a first resistor connected between a first potential point and the output of the capacitor, a second resistor connected between a second potential point and the output of the capacitor, and a limiter connected to the output of the capacitor.
    Type: Grant
    Filed: March 21, 1979
    Date of Patent: September 8, 1981
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Ikio Yoshida, Kouzou Kage, Kazuhiro Ikeda, Yasuo Sato
  • Patent number: 4227251
    Abstract: A clock pulse regenerator is constructed with digital circuits and may be built using large scale integration techniques. An oscillator produces first pulses at a repetition rate higher than that of the incoming digital data signal. A first counter counts the first pulses to produce the regenerated clock pulses. A gate pulse generator is responsive to both the incoming digital data signal and the regenerated clock pulses to generate a gate pulse having a pulse width proportional to a phase difference between the two signals. A third counter counts the number of leading and trailing edges of the incoming digital data signal. The pulse outputs of the second and third counters are supplied to a gate circuit. A fourth counter counts the pulses transmitted by the gate circuit to produce, after a predetermined count, a reset pulse for the first, second, third and fourth counters. The second, third and fourth counters therefore serve as a phase detector.
    Type: Grant
    Filed: December 13, 1978
    Date of Patent: October 7, 1980
    Assignees: Nippon Telegraph and Telephone Public Corporation, Nippon Electric Co., Ltd.
    Inventors: Shigeru Kazama, Kouzou Kage
  • Patent number: 4204170
    Abstract: An impulse noise limiter circuit comprises a delay circuit for delaying a signal containing impulse noise and a clamp circuit provided between the input and output terminals of the delay circuit for limiting the voltage difference between the terminals to a given value.
    Type: Grant
    Filed: January 6, 1978
    Date of Patent: May 20, 1980
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Kouzou Kage
  • Patent number: 4204164
    Abstract: A noise detector circuit for radio receivers is disclosed. The circuit includes a delay circuit for slightly delaying a received signal. A comparator compares the level of the received signal with the delayed signal to generate a pulse sequence having a number of pulses per unit that is proportional to the level of said noise. A counter counts the number of pulses to detect the level of the noise in the received signal.
    Type: Grant
    Filed: August 3, 1978
    Date of Patent: May 20, 1980
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Kouzou Kage
  • Patent number: 4128809
    Abstract: Responsive to several signal bits carrying an information piece and received with inevitable fluctuations of the signal bit widths and height, a time diversity receiver reproduces the information piece by mainly taking the widest or highest signal bit into consideration. In order to give significance to the widest or highest signal bit, the signal bit levels are added for each information piece. When high-frequency pulses are used to derive the sum width of the signal bit widths, it is preferred to substitute pulses of a frequency equal to a half or so of the high frequency for the high-frequency pulses representative of the width of the signal bit or bits received with serious fluctuations. Alternatively, the transmitter carries out the reproduction by attaching importance to the signal bit received with smallest fluctuations either solely or together with the preference or weight put on the widest or highest signal bit.
    Type: Grant
    Filed: August 31, 1977
    Date of Patent: December 5, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Kouzou Kage
  • Patent number: 4105979
    Abstract: A clock regenerator for an input data signal varying between a high and a low level at one or more bit periods comprises a controllable frequency divider for frequency dividing a local signal of a high frequency at a frequency division ratio into a regenerated clock signal. When the regenerated clock signal has a leading and a lagging phase difference relative to the input data signal, a counter preset once in every regenerated clock period with a reference value for the frequency division ratio up-counts and down-counts, respectively, the reference value as a function of the amount of the phase difference to control the frequency division ratio.
    Type: Grant
    Filed: May 2, 1977
    Date of Patent: August 8, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Kouzou Kage