Patents by Inventor Kouzou Mawatari

Kouzou Mawatari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140332846
    Abstract: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Inventors: Tsutomu Imoto, Kouzou Mawatari
  • Patent number: 8093623
    Abstract: Disclosed herein is a semiconductor integrated circuit including a protected circuit; and a protection element formed on the same semiconductor substrate as the protected circuit and adapted to protect the protected circuit, wherein the protection element includes two diodes having their anodes connected together to form a floating node and two cathodes connected to the protected circuit, the two diodes are formed in a well-in-well structure on the semiconductor substrate, and the well-in-well structure includes a P-type well forming the floating gate, an N-type well which surrounds the surfaces of the P-type well other than that on the front side of the substrate with the deep portion side of the substrate so as to form the cathode of one of the diodes, and a first N-type region formed in the P-type well so as to form the cathode of the other diode.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: January 10, 2012
    Assignee: Sony Corporation
    Inventors: Kouzou Mawatari, Motoyasu Yano
  • Publication number: 20100133583
    Abstract: Disclosed herein is a semiconductor integrated circuit including a protected circuit; and a protection element formed on the same semiconductor substrate as the protected circuit and adapted to protect the protected circuit, wherein the protection element includes two diodes having their anodes connected together to form a floating node and two cathodes connected to the protected circuit, the two diodes are formed in a well-in-well structure on the semiconductor substrate, and the well-in-well structure includes a P-type well forming the floating gate, an N-type well which surrounds the surfaces of the P-type well other than that on the front side of the substrate with the deep portion side of the substrate so as to form the cathode of one of the diodes, and a first N-type region formed in the P-type well so as to form the cathode of the other diode.
    Type: Application
    Filed: November 2, 2009
    Publication date: June 3, 2010
    Applicant: Sony Corporation
    Inventors: Kouzou Mawatari, Motoyasu Yano
  • Publication number: 20100078724
    Abstract: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: SONY CORPORATION
    Inventors: Tsutomu Imoto, Kouzou Mawatari