Patents by Inventor Kouzou Sakamoto

Kouzou Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6028573
    Abstract: In a method for driving a display device, by which energy stored in a plurality of electrodes serving as a capacitive load is recovered through switches, current paths for charging said electrodes from a charge supplying source differ from current paths for discharging the electrodes for the energy recovery.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: February 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Isamu Orita, Akihiko Kougami, Shigeo Mikoshiba, Takeaki Okabe, Kouzou Sakamoto, Masahiro Eto
  • Patent number: 6008687
    Abstract: A switching circuit has switching elements for passing-through or cutting-off signals of a positive pulse, which is a rectangular pulse rising from a low level and falling after having kept a high level for a certain time as a high voltage input signal, and a negative pulse, which is a rectangular pulse falling from a high level and rising after having kept a low level for a certain time, the switching circuit being applied to a capacitive load driving device.
    Type: Grant
    Filed: November 29, 1996
    Date of Patent: December 28, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Isamu Orita, Akihiko Kougami, Shigeo Mikoshiba, Takeaki Okabe, Kouzou Sakamoto, Masahiro Eto
  • Patent number: 5379230
    Abstract: A semiconductor integrated circuit has a semiconductor output device (3) , a sensor (5) generating an electric signal (7) relevant to heat generation (6) of the output device (3) and a microprocessor unit MPU 2, inside a chip (1). The MPU (2) is constructed of a memory (20) and CPU (22). The electric signal (7) generated from the sensor (5) is processed by the CPU (22) in accordance with a stored program of the memory (20). Accordingly, the drivability of the semiconductor output device (3) can be set in an optimum state corresponding to changes in chip temperature including changes that are only momentary.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: January 3, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Morikawa, Isao Yoshida, Terumi Sawase, Kouzou Sakamoto, Takeaki Okabe
  • Patent number: 5299091
    Abstract: A packaged semiconductor device has, according to one embodiment of the present invention, a semiconductor pellet having an electronic circuit therein and electrode pads formed on a principal surface of the pellet, a plurality of electrical connection bumps provided on the electrode pads, a plurality of heat dissipation bumps provided at the principal surface of the pellet and electrically insulated from the electronic circuit and the electrode pads, electrical connection leads for the electronic circuit, heat dissipators for the electronic circuit and a packaging material for sealing pellet, the electrical connection bumps, the heat dissipation bumps and parts of the electrical connection leads and the heat dissipator. One or more of the heat dissipation bumps are arranged relatively nearer to the electronic circuit than the electrical connection bumps for thermal coupling to the electronic circuit.
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: March 29, 1994
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Akio Hoshi, Yukihiro Sato, Toyomasa Koda, Isao Yoshida, Kouzou Sakamoto
  • Patent number: 4814288
    Abstract: A method of fabricating semiconductor devices which include vertical elements and control elements. A well is formed by etching in a semiconductor substrate of a first conductivity type, and a first epitaxial layer having a second conductivity type opposite to the first conductivity type is epitaxially grown, followed by etching and/or grinding and/or polishing to fill said well. Further, a second epitaxial layer of the first conductivity type is epitaxially grown on the substrate and on the first epitaxial layer, and an impurity-doped layer of the second conductivity type for isolation is formed in the second epitaxial layer to penetrate therethrough. A first element is formed in the second epitaxial layer in a portion that corresponds to the well, and a second element having a vertical structure and having a current capability higher than that of the first element is formed except a portion of the second epitaxial layer that corresponds to the well.
    Type: Grant
    Filed: July 10, 1987
    Date of Patent: March 21, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Kimura, Takeaki Okabe, Isao Yoshida, Kouzou Sakamoto, Kazuo Hoya, Kouichiro Satonaka, Toyomasa Koda, Shigeo Ohtaka