Abstract: An externally triggered memory type liquid crystal thin film is provided with a wireless communication module including first and second driver units wherein a current is generated in the second driver unit when a distance between the first driver unit and the second driver unit is equal to or less than a predetermined value; and a light adjustment module including a first conduction layer electrically connected to a first terminal of the second driver unit so that the second driver unit supplies the current to the first conduction layer, a second conduction layer electrically connected to a second terminal of the second driver unit, and a liquid crystal layer formed between the first and second conduction layers so that an electric field is generated in the liquid crystal layer by both the first and second conduction layers.

Abstract: This invention relates to a process for fabricating a staggered source/drain and thin-channel TFT structure, which simplifies the conventional process for fabricating the structure by decreasing the number of mask steps and achieving better results at suppressing the electric field near the drain junction and reducing the leakage current. The process comprises (1) re-crystallizing a-Si into poly-Si (02), which is performed by depositing an a-Si layer on a substrate and then applying a general photolithographic step and a RIE etching step for defining the amorphous Si islands provided with higher regions and lower regions, wherein the residual width of the thin channel of the a-Si is about 5 to 200 nm after etching; then the a-Si is changed into poly-Si (02) after a subsequent annealing; (2) defining the gate region (05), source/drain region (07) and the channel; (3) applying the implantation; and (4) applying the connection.

Abstract: This invention relates to a process for fabricating a staggered source/drain and thin-channel TFT structure, which simplifies the conventional process for fabricating the structure by decreasing the number of mask steps and achieving better results at suppressing the electric field near the drain junction and reducing the leakage current. The process comprises (1) re-crystallizing a-Si into poly-Si (02), which is performed by depositing an a-Si layer on a substrate and then applying a general photolithographic step and a RIE etching step for defining the amorphous Si islands provided with higher regions and lower regions, wherein the residual width of the thin channel of the a-Si is about 5 to 200 nm after etching; then the a-Si is changed into poly-Si (02) after a subsequent annealing; (2) defining the gate region (05), source/drain region (07) and the channel; (3) applying the implantation; and (4) applying the connection.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior arts is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior art is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior art is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior art is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

Abstract: A semiconductor structure with a dielectric layer and its producing method are disclosed. The semiconductor structure includes a semiconductor substrate having thereon a plurality of metal lines and there are a plurality of concave regions formed between the metal lines. The dielectric layer is formed on the semiconductor by a method which can prevent the dielectric material from flowing into the concave regions. The method includes the steps of (a) providing a semiconductor substrate having thereon a plurality of metal lines forming therebetween a plurality of concave regions; and (b) forming the dielectric layer on the metal lines. The concave regions are only filled with air so that the capacitance of the semiconductor is lowered.

Abstract: A method is described for manufacturing an oxide layer. A substrate is provided. An amorphous silicon layer is formed on the substrate. The amorphous silicon layer is recrystallized to form a polysilicon layer. The polysilicon layer is oxidized to form an oxide layer.

Abstract: A structure and producing method of a three-electrode capacitive pressure sensor can integrate and produce sensor capacitor and reference capacitor in the same pressure sensor cavity. This dual capacitor integration structure can cancel off environment interference of the same mode by differentiated circuit. Avoiding connection between upper and lower electrode plates can be achieved through the existence of a third electrode plate. In working pressure interval from 25 psi to 40 psi, the sensitivity of said three-electrode capacitive sensor is a 0.21 pF/psi, while the sensitivity of an ordinary planar connection pressure sensor is 0.05 pF/psi. The merits of said three-electrode capacitive pressure sensor include trivial production procedure and connection with planar and high sensitivity.

Abstract: Provided a process for producing a refractory metal by chemical vapor deposition of a bilayer-stacked tungsten metal by depositing a bilayer-stacked tungsten metal in a same chamber in the manner of not breaking the vacuum therein. Firstly, a layer of amorphous-like tungsten is deposited to increase thermal stability and to prevent diffusion of fluorine atom. Next, a nitridizing treatment is performed thereon to promote further the barrier property and thermal stability of the amorphous-like tungsten. Finally, conventional selective chemical vapor deposited tungsten having low is deposited on the amorphous-like tungsten. Through the deposition of bilayer tungsten according to the process of the invention, thermal stability of conventional selective chemical vapor deposited tungsten can be increased greatly.

Abstract: A method is provided for fabricating a tunneling oxide layer over a semiconductor substrate with a textured surface. The method is suitable for a semiconductor substrate, such as a silicon substrate, having a polysilicon layer formed over the substrate. The method has several steps of performing a thermal oxidation process to over oxidize the polysilicon layer so as to form an interfacial oxide layer between the substrate and the polysilicon layer, which actually is oxidized as an oxide layer. Due to material property of polysilicon, a textured surface is naturally formed on a top of the substrate. After removing the oxide layer and the interfacial oxide layer, a tunneling oxide layer is formed over the substrate with the textured surface.

Abstract: A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower impurity concentration. The first doped region formed on the substrate by a high-energy ion-implantation process is kept at a predetermined distance from the surface of the substrate. The second doped region extends from the surface of the substrate toward the downside to connect to the first doped region, such that two third doped regions are formed. The second doped region is formed by an ion-implantation process through an opening of a mask. Furthermore, a gate is formed above the second doped region, and source and drain regions are formed on the substrate. Therefore, a device having an inverse T-shaped well region is completely fabricated.

Abstract: A structure for reducing the stress between a HSQ dielectric layer and a metal layer. The structure comprises a metal layer, a stress buffer above the metal layer, and a spin-on-glass layer above the stress buffer. If the spin-on-glass layer is a dielectric material capable of producing tensile stress, the stress buffer layer is made from a material capable of generating compressive stress. On the contrary, if the spin-on-glass layer is a dielectric material capable of producing compressive stress, the stress buffer layer is made from a material capable of generating tensile stress.