Patents by Inventor Koya SHIMAZAKI

Koya SHIMAZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072792
    Abstract: A semiconductor device includes two power-on reset (POR) circuits having different response characteristics to a change in power voltage in generating and outputting a reset signal by detecting a change in voltage value of the power voltage, and a selector. The selector selects a reset signal outputted from one of the two POR circuits based on an inputted selection control signal, and outputs the selected signal as a reset signal.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Koya SHIMAZAKI
  • Patent number: 11804425
    Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 31, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Koya Shimazaki
  • Publication number: 20230099673
    Abstract: A semiconductor device includes a semiconductor IC, a capacitor element, a support portion, a first conductor and second conductor, and a sealing body. The semiconductor IC has a first IC terminal and a second IC terminal. The capacitor element has a first terminal and a second terminal. The support portion supports the capacitor element and the semiconductor IC. The first conductor and second conductor extend so as to connect the first terminal and second terminal with, respectively, the first IC terminal and second IC terminal. The sealing body encloses the capacitor element, the semiconductor IC, the first conductor, the second conductor and the support portion. The first IC terminal and second IC terminal, the first terminal and second terminal, the first conductor and the second conductor are disposed at the inner side relative to an outer edge of the support portion.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 30, 2023
    Inventor: KOYA SHIMAZAKI
  • Publication number: 20210391241
    Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventor: KOYA SHIMAZAKI
  • Patent number: 11133243
    Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: September 28, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Koya Shimazaki
  • Publication number: 20190333844
    Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 31, 2019
    Inventor: KOYA SHIMAZAKI
  • Patent number: 9054662
    Abstract: An automatic audio signal level adjustment circuit is capable of automatically adjusting a level of an input audio signal within a specific range. The automatic audio signal level adjustment circuit includes an amplitude adjustment determining unit and an amplitude adjusting unit. The amplitude adjustment determining unit is configured to generate an amplitude reduction instruction when the level is greater than a first reference value, and an amplitude augmentation instruction when the level is small than a second reference value. The amplitude adjusting unit is configured to output an output audio signal having an amplitude reduced from that of the input audio signal upon the amplitude reduction instruction, and an output audio signal having an amplitude augmented from that of the input audio signal upon the amplitude augmentation instruction. Further, the amplitude adjusting unit is configured to output an output audio signal equal to the input audio signal upon no instruction.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 9, 2015
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Koya Shimazaki
  • Publication number: 20120163631
    Abstract: An automatic audio signal level adjustment circuit is capable of automatically adjusting a level of an input audio signal within a specific range. The automatic audio signal level adjustment circuit includes an amplitude adjustment determining unit and an amplitude adjusting unit. The amplitude adjustment determining unit is configured to generate an amplitude reduction instruction when the level is greater than a first reference value, and an amplitude augmentation instruction when the level is small than a second reference value. The amplitude adjusting unit is configured to output an output audio signal having an amplitude reduced from that of the input audio signal upon the amplitude reduction instruction, and an output audio signal having an amplitude augmented from that of the input audio signal upon the amplitude augmentation instruction. Further, the amplitude adjusting unit is configured to output an output audio signal equal to the input audio signal upon no instruction.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 28, 2012
    Inventor: Koya SHIMAZAKI