Abstract: This invention introduces a resistive random access memory (RRAM) device, a write verify method and a reverse write verify thereof which are capable of improving the performance of RRAM operations and improving the uniform performance for each RRAM cell. A first resistance value sensed from a RRAM cell is compared with a plurality of reference resistance values to obtain a comparison value. A set or a reset operation is performed on the RRAM cell by applying a first set or reset pulse to change the first resistance value to a second resistance value. Next, the second resistance value is compared with the comparison value to determine whether to continue the set or reset operation on the RRAM cell.

Abstract: A memory device and a data reading method are provided. A dummy circuit performs a read operation in synchronism with a data access circuit according to an address signal, so as to estimate time points at which the data access circuit completes each of operating procedures, and enable the data access circuit to execute a next operating procedure when completing an operating procedure.

Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.

Abstract: In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of VCC values without wasted time by allocating a predetermined number of clocks to the combined operations rather than to the individual operations and operating at higher frequency for high VCC values, and lower frequency for low VCC values.

Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.

Abstract: In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of VCC values without wasted time by allocating a predetermined number of clocks to the combined operations rather than to the individual operations and operating at higher frequency for high VCC values, and lower frequency for low VCC values.

Abstract: A resistive random-access memory device includes a RRAM array including a plurality of RRAM cells coupled to a source line, a controller, a bit-line decoder, and a sense circuit. Each of the RRAM cells storing a logic state and is selected by the corresponding bit line and word line. The controller selects a selected RRAM cell by a bit-line signal and a selected word line and determines the logic state according to a sense signal. The bit-line decoder couples a data bit line to the selected bit line according to a bit-line signal. The sense circuit is coupled to the data bit line and compares a memory current flowing through the selected RRAM with a reference current to generate the sense signal. The sense circuit sinks the memory current from the data bit line when operating in a reset operation and a reverse read operation.

Abstract: A resistive random-access memory device includes a RRAM array including a plurality of RRAM cells coupled to a source line, a controller, a bit-line decoder, and a sense circuit. Each of the RRAM cells storing a logic state and is selected by the corresponding bit line and word line. The controller selects a selected RRAM cell by a bit-line signal and a selected word line and determines the logic state according to a sense signal. The bit-line decoder couples a data bit line to the selected bit line according to a bit-line signal. The sense circuit is coupled to the data bit line and compares a memory current flowing through the selected RRAM with a reference current to generate the sense signal. The sense circuit sinks the memory current from the data bit line when operating in a reset operation and a reverse read operation.

Abstract: A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.

Abstract: A NVM apparatus and an operation method thereof are provided. The NVM apparatus includes a NVM cell, a programming voltage generator, a WL-voltage generator and a CSL-voltage generator. A control terminal, and a first and second terminals of the NVM cell are electrically connected to a word line, a bit line and a common source line, respectively. The programming voltage generator provides a programming voltage to the bit line and detects a current thereof. The WL-voltage generator provides a WL-voltage to the word line, where a switch of the WL-voltage is a word line high voltage to a word line low voltage. The CSL-voltage generator provides a CSL-voltage to the common source line. According to the current of the bit line, the WL-voltage generator dynamical adjusts the word line low voltage, or the CSL-voltage generator dynamically adjusts the CSL-voltage.

Abstract: A writing and verifying circuit and a method for writing and verifying a resistive memory thereof are provided. The steps of the method includes: enabling at least one word line signal corresponding to at least one selected resistive memory cell of the resistive memory during a writing and verifying timing period; providing a bit line voltage to the selected resistive memory cells, wherein the bit line voltage continuously increases or decreases from a first voltage level to a second voltage level during the writing and verifying timing period; and, measuring a detected current through the bit line and determining a finish time point of the writing and verifying timing period according to the detected current and a reference current.

Abstract: A drain regulator for a NOR flash memory includes a pump source, a pass transistor, a voltage divider, a Y-path gate, an amplifier, and a current detector. The pump source is configured to pump a supply voltage to a high voltage at a HV node. The pass transistor is coupled between the HV node and a bit line. The pass transistor is controlled by a control signal to generate a bit-line voltage at the bit line. The voltage divider divides the bit-line voltage by a factor to generate a feedback voltage at a feedback node. The Y-path gate biases the selected cell with a drain voltage. The amplifier supplied with the HV voltage compares the feedback voltage with a reference voltage to generate the control signal. The current detector senses a current flowing through the Y-path gate to generate a sense signal to the feedback node.

Abstract: A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.

Abstract: A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.

Abstract: A method of erasing a target erase area of a non-volatile memory is provided, wherein the non-volatile memory is divided into an target erase area and an unselected area, and the method includes the steps in an erase cycle of: conditioning the target erase area of the non-volatile memory, wherein the unselected area is an area, excluding the target erase area, in the non-volatile memory; erasing target cells of the target erase area, wherein the threshold of the target cells is not greater than an erase verify voltage; soft-programming the target cells, wherein the threshold of the target cells is not less than a soft program verify voltage, wherein the soft program verify voltage is less than the erase verify voltage; and refreshing a predefined portion of the unselected area, wherein the predefined portion in the erase cycle is less than the unselected area.

Abstract: A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required.

Abstract: A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required.

Abstract: A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.