Patents by Inventor Koyu Asai

Koyu Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8084343
    Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Yamaguchi, Koyu Asai, Mahito Sawada, Kiyoteru Kobayashi, Tatsunori Murata, Satoshi Shimizu
  • Publication number: 20110092037
    Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
    Type: Application
    Filed: December 23, 2010
    Publication date: April 21, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadashi Yamaguchi, Koyu Asai, Mahito Sawada, Kiyoteru Kobayashi, Tatsunori Murata, Satoshi Shimizu
  • Patent number: 7875539
    Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Yamaguchi, Koyu Asai, Mahito Sawada, Kiyoteru Kobayashi, Tatsunori Murata, Satoshi Shimizu
  • Patent number: 7759722
    Abstract: When microfabrication is done, a reliable semiconductor device is offered. A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface and the side surface of each of a plurality of convex patterns might be covered, and so that width might become large rather than the portion which covers the lower part side surface of a convex pattern in the portion which covers an upper part side surface, and a second insulating film that covers the upper surface and the side surface of the first insulating film so that the cavity between the adjacent convex patterns may be occluded. The position occluded by the second insulating film of a cavity is a position higher than the upper surface of a floating gate, and is a position lower than the upper surface of a control gate.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tatsunori Murata, Koyu Asai, Hiroaki Iuchi
  • Patent number: 7489040
    Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: February 10, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Koyu Asai, Hiroshi Tobimatsu, Hiroyuki Kawata, Mahito Sawada
  • Publication number: 20090017614
    Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
    Type: Application
    Filed: September 19, 2008
    Publication date: January 15, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tadashi Yamaguchi, Koyu Asai, Mahito Sawada, Kiyoteru Kobayashi, Tatsunori Murata, Satoshi Shimizu
  • Publication number: 20080014760
    Abstract: When microfabrication is done, a reliable semiconductor device is offered. A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface and the side surface of each of a plurality of convex patterns might be covered, and so that width might become large rather than the portion which covers the lower part side surface of a convex pattern in the portion which covers an upper part side surface, and a second insulating film that covers the upper surface and the side surface of the first insulating film so that the cavity between the adjacent convex patterns may be occluded. The position occluded by the second insulating film of a cavity is a position higher than the upper surface of a floating gate, and is a position lower than the upper surface of a control gate.
    Type: Application
    Filed: June 20, 2007
    Publication date: January 17, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Tatsunori MURATA, Koyu Asai, Hiroaki Iuchi
  • Publication number: 20070096322
    Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
    Type: Application
    Filed: December 8, 2006
    Publication date: May 3, 2007
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Koyu Asai, Hiroshi Tobimatsu, Hiroyuki Kawata, Mahito Sawada
  • Publication number: 20070049046
    Abstract: The present invention aims at offering the filled structure of an oxide film etc. which can form an insulating film (oxide film) without void in a predetermined depressed portion by an economical and practical method and without increasing RF bias. According to the first invention, the oxide film filled structure is provided with the foundation (silicon substrate) having a depressed portion (trench), and the oxide film (silicon oxide film) formed in the depressed portion concerned. Here, the oxide film concerned includes the silicon oxide film region of silicon-richness in part at least.
    Type: Application
    Filed: August 11, 2006
    Publication date: March 1, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Mahito Sawada, Koyu Asai, Yoshihiro Miyagawa, Tatsunori Murata
  • Patent number: 7154184
    Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: December 26, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Koyu Asai, Hiroshi Tobimatsu, Hiroyuki Kawata, Mahito Sawada
  • Publication number: 20060091451
    Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
    Type: Application
    Filed: October 21, 2005
    Publication date: May 4, 2006
    Inventors: Tadashi Yamaguchi, Koyu Asai, Mahito Sawada, Kiyoteru Kobayashi, Tatsunori Murata, Satoshi Shimizu
  • Publication number: 20040251555
    Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
    Type: Application
    Filed: December 3, 2003
    Publication date: December 16, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Koyu Asai, Hiroshi Tobimatsu, Hiroyuki Kawata, Mahito Sawada