Patents by Inventor Kozaburo Kurita
Kozaburo Kurita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9291671Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).Type: GrantFiled: November 19, 2013Date of Patent: March 22, 2016Assignee: Hitachi, Ltd.Inventors: Yasuyoshi Sunaga, Hideki Sakakibara, Yuko Ito, Tomoji Nakamura, Atsushi Hazeyama, Kozaburo Kurita, Koki Tsutsumida
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Publication number: 20140070863Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).Type: ApplicationFiled: November 19, 2013Publication date: March 13, 2014Applicant: Hitachi, Ltd.Inventors: Yasuyoshi Sunaga, Hideki Sakakibara, Yuko Ito, Tomoji Nakamura, Atsushi Hazeyama, Kozaburo Kurita, Koki Tsutsumida
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Publication number: 20110074385Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).Type: ApplicationFiled: August 3, 2010Publication date: March 31, 2011Inventors: Yasuyoshi Sunaga, Hideki Sakakibara, Yuko Ito, Tomoji Nakamura, Atsushi Hazeyama, Kozaburo Kurita, Koki Tsutsumida
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Patent number: 7777331Abstract: A semiconductor apparatus including built-in power supply circuits capable of supplying a large current with high voltage accuracy. The semiconductor apparatus includes a semiconductor chip including a circuit area and power supply circuits, coils and capacitors. The semiconductor chip, coils and capacitors are provided in a package. Each power supply circuit, a coil and a capacitor compose a switching regulator. The semiconductor chip and the package are connected such that a power supply voltage which will be produced by the switching regulator is supplied to the circuit area. The power supply circuit is supplied with a power supply voltage from the outside of the semiconductor apparatus.Type: GrantFiled: June 12, 2007Date of Patent: August 17, 2010Assignee: Hitachi, Ltd.Inventor: Kozaburo Kurita
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POWER-SUPPLY DEVICE, IC CIRCUIT, AND INFORMATION PROCESSING APPARATUS, AND SOFT-START CONTROL METHOD
Publication number: 20090021227Abstract: An electric current flowing to an upper side power MOSFET during soft-start is detected according to an on-voltage of the MOSFET and an on-pulse width of a PWM pulse for driving the upper side power MOSFET is forced to be reset in the idle and decided according to a signal generated when the voltage falls below a predetermined specified voltage.Type: ApplicationFiled: January 25, 2008Publication date: January 22, 2009Inventors: Takashi Sase, Yosuke Kawakubo, Kozaburo Kurita -
Patent number: 7403365Abstract: An over-current detection circuit using the ON-voltage of a main MOSFET is provided, which is resistant to process variations of a main MOSFET and is not easily influenced by switching noise. Separately from a main MOSFET (Q1), a sense MOSFET (Q3) whose size is 1/m of the main MOSFET is provided and it is caused to be normally on. A DC ON-voltage generated when a current that is 1/m of an over-current value is caused to flow through the sense MOSFET is obtained as a reference voltage for over-current setting. The ON-voltage when the main MOSFET is on is sampled and held, and it is obtained as a DC voltage. These DC voltages are compared in a comparator (COMP).Type: GrantFiled: August 18, 2006Date of Patent: July 22, 2008Assignee: Hitachi, Ltd.Inventors: Takashi Sase, Akihiko Kanouda, Yosuke Kawakubo, Kozaburo Kurita
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Publication number: 20070300092Abstract: A semiconductor apparatus including built-in power supply circuits capable of supplying a large current with high voltage accuracy. The semiconductor apparatus includes a semiconductor chip including a circuit area and power supply circuits, coils and capacitors. The semiconductor chip, coils and capacitors are provided in a package. Each power supply circuit, a coil and a capacitor compose a switching regulator. The semiconductor chip and the package are connected such that a power supply voltage which will be produced by the switching regulator is supplied to the circuit area. The power supply circuit is supplied with a power supply voltage from the outside of the semiconductor apparatus.Type: ApplicationFiled: June 12, 2007Publication date: December 27, 2007Inventor: Kozaburo KURITA
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Publication number: 20070188958Abstract: An over-current detection circuit using the ON-voltage of a main MOSFET is provided, which is resistant to process variations of a main MOSFET and is not easily influenced by switching noise. Separately from a main MOSFET (Q1), a sense MOSFET (Q3) whose size is 1/m of the main MOSFET is provided and it is caused to be normally on. A DC ON-voltage generated when a current that is 1/m of an over-current value is caused to flow through the sense MOSFET is obtained as a reference voltage for over-current setting. The ON-voltage when the main MOSFET is on is sampled and held, and it is obtained as a DC voltage. These DC voltages are compared in a comparator (COMP).Type: ApplicationFiled: August 18, 2006Publication date: August 16, 2007Applicant: Hitachi, Ltd.Inventors: Takashi Sase, Akihiko Kanouda, Yosuke Kawakubo, Kozaburo Kurita
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Patent number: 7113434Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: GrantFiled: April 14, 2004Date of Patent: September 26, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Patent number: 7111187Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.Type: GrantFiled: November 6, 2003Date of Patent: September 19, 2006Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Patent number: 7078928Abstract: The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.Type: GrantFiled: December 17, 2003Date of Patent: July 18, 2006Assignee: Hitachi, Ltd.Inventors: Ryusuke Sahara, Kozaburo Kurita, Yuuji Suzuki, Mitsugu Kusunoki, Hideki Sakakibara
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Patent number: 6947514Abstract: A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.Type: GrantFiled: June 26, 1998Date of Patent: September 20, 2005Assignee: Renesas Technology CorporationInventors: Kazuo Kato, Takashi Sase, Takashi Hotta, Hirokazu Aoki, Kozaburo Kurita
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Publication number: 20040196080Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: ApplicationFiled: April 14, 2004Publication date: October 7, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Publication number: 20040128635Abstract: The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.Type: ApplicationFiled: December 17, 2003Publication date: July 1, 2004Inventors: Ryusuke Sahara, Kozaburo Kurita, Yuuji Suzuki, Mitsugu Kusunoki, Hideki Sakakibara
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Publication number: 20040093532Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.Type: ApplicationFiled: November 6, 2003Publication date: May 13, 2004Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-Ichi Sinoda
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Patent number: 6735129Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: GrantFiled: May 24, 2002Date of Patent: May 11, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Patent number: 6675311Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.Type: GrantFiled: December 6, 2001Date of Patent: January 6, 2004Assignee: HItachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Publication number: 20020176292Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.Type: ApplicationFiled: May 24, 2002Publication date: November 28, 2002Applicant: Hitachi, Ltd.Inventors: Hiroshi Akasaki, Shuichi Miyaoka, Yuji Yokoyama, Masatoshi Hasegawa, Kozaburo Kurita
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Publication number: 20020059538Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1. and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.Type: ApplicationFiled: December 6, 2001Publication date: May 16, 2002Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-Ichi Sinoda
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Publication number: 20010045849Abstract: A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects that the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcedly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit.Type: ApplicationFiled: November 17, 1999Publication date: November 29, 2001Inventor: KOZABURO KURITA