Patents by Inventor Kozo Ishikawa
Kozo Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9515170Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.Type: GrantFiled: February 5, 2016Date of Patent: December 6, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshiaki Iwamatsu, Takashi Terada, Hirofumi Shinohara, Kozo Ishikawa, Ryuta Tsuchiya, Kiyoshi Hayashi
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Publication number: 20160155825Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.Type: ApplicationFiled: February 5, 2016Publication date: June 2, 2016Inventors: Toshiaki IWAMATSU, Takashi TERADA, Hirofumi SHINOHARA, Kozo ISHIKAWA, Ryuta TSUCHIYA, Kiyoshi HAYASHI
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Patent number: 9287400Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.Type: GrantFiled: August 16, 2012Date of Patent: March 15, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshiaki Iwamatsu, Takashi Terada, Hirofumi Shinohara, Kozo Ishikawa, Ryuta Tsuchiya, Kiyoshi Hayashi
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Patent number: 8754471Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.Type: GrantFiled: March 4, 2011Date of Patent: June 17, 2014Assignee: Renesas Electronics CorporationInventors: Toshiaki Iwamatsu, Kozo Ishikawa, Masashi Kitazawa, Kiyoshi Hayashi, Takahiro Maruyama, Masaaki Shinohara, Kenji Kawai
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Patent number: 8492230Abstract: To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin.Type: GrantFiled: August 31, 2010Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventors: Kozo Ishikawa, Masaaki Shinohara, Toshiaki Iwamatsu
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Publication number: 20120309157Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.Type: ApplicationFiled: August 16, 2012Publication date: December 6, 2012Inventors: Toshiaki IWAMATSU, Takashi TERADA, Hirofumi SHINOHARA, Kozo ISHIKAWA, Ryuta TSUCHIYA, Kiyoshi HAYASHI
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Patent number: 8269288Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.Type: GrantFiled: October 17, 2008Date of Patent: September 18, 2012Assignee: Renesas Electronics CorporationInventors: Toshiaki Iwamatsu, Takashi Terada, Hirofumi Shinohara, Kozo Ishikawa, Ryuta Tsuchiya, Kiyoshi Hayashi
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Publication number: 20110215423Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.Type: ApplicationFiled: March 4, 2011Publication date: September 8, 2011Inventors: Toshiaki IWAMATSU, Kozo ISHIKAWA, Masashi KITAZAWA, Kiyoshi HAYASHI, Takahiro MARUYAMA, Masaaki SHINOHARA, Kenji KAWAI
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Publication number: 20110049629Abstract: To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Inventors: Kozo Ishikawa, Masaaki Shinohara, Toshiaki Iwamatsu
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Publication number: 20110031552Abstract: To provide, in FINFET whose threshold voltage is determined essentially by the work function of a gate electrode, a technology capable of adjusting the threshold voltage of FINFET without changing the material of the gate electrode. FINFET is formed over an SOI substrate comprised of a substrate layer, a buried insulating layer formed over the substrate layer, and a silicon layer formed over the buried insulating layer. The substrate layer has therein a first semiconductor region contiguous to the buried insulating layer. The silicon layer of the SOI substrate is processed into a fin. A ratio of the height of the fin to the width of the fin is adjusted to fall within a range of from 1 or greater but not greater than 2. In addition, a voltage can be applied to the first semiconductor region.Type: ApplicationFiled: August 6, 2010Publication date: February 10, 2011Inventors: Toshiaki IWAMATSU, Kozo Ishikawa, Kiyoshi Hayashi
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Publication number: 20090101977Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.Type: ApplicationFiled: October 17, 2008Publication date: April 23, 2009Inventors: Toshiaki Iwamatsu, Takashi Terada, Hirofumi Shinohara, Kozo Ishikawa, Ryuta Tsuchiya, Kiyoshi Hayashi
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Patent number: 4307859Abstract: An automatic message announcement system for trains in the railroad station premises, including a train tracking circuit which tracks the location of approaching train, a trains information memory which stores information concerning each train, an edition circuit which combines the train information read out from said train information memory and a series of message patterns which include portions to be completed and which edits the message patterns to produce a series of short messages arranged sequentially according of their priority order to the content, an announcement message selection circuit which determines up to which short message among those arranged sequentially according to said priority order should be announced, in accordance with the location of the train at the time the announcement starts, and an automatic announcement system which includes a voice memory containing addressable voice segments for annoucing the message determined above.Type: GrantFiled: February 13, 1980Date of Patent: December 29, 1981Assignees: Japanese National Railways, Fujitsu Limited, Fujitsu Kiden Ltd.Inventors: Yoshiro Hayashi, Akira Sugihara, Takaki Shimura, Kozo Ishikawa, Kiyoshi Wada, Eiji Yamanaka, Shunsuke Senba
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Patent number: 4276572Abstract: An automatic message announcement system for announcing the approach, arrival, and departure of vehicles such as trains at a train station. An addressable voice memory is provided for storing sequences of voice segments which are read out upon receipt of announcement command input signals to form messages for announcing that a vehicle is approaching or has arrived or is departing, with specific information such as the vehicle's destination being included in the announcement by inserting the appropriate voice segments at the proper points in the sequence. The messages are composed in such a manner that the sequences of voice segments can be altered to form shorter, but still intelligible, messages if vehicles traffic is so heavy that one message is due for announcement before the previous announcement is completed.Type: GrantFiled: October 26, 1979Date of Patent: June 30, 1981Assignees: Japanese National Railways, Fujitsu Limited, Fujitsu Kiden Ltd.Inventors: Yoshiro Hayashi, Akira Sugihara, Takaki Shimura, Kozo Ishikawa, Kiyoshi Wada, Eiji Yamanaka, Shunsuke Senba