Patents by Inventor Kozo Kinoshita

Kozo Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250061336
    Abstract: According to an embodiment, an information processing apparatus includes a processing unit configured to: detect whether or not one or more conditions defining timings to perform learning of a regression model configured to predict one or more objective variables for a plurality of explanatory variables are satisfied; determine priorities of the plurality of explanatory variables according to a condition detected to be satisfied; and perform learning of the regression model by using an objective function and learning data, the objective function including a regularization term having a regularization strength changing according to the priorities.
    Type: Application
    Filed: February 29, 2024
    Publication date: February 20, 2025
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masaaki TAKADA, Gen LI, Yasuhisa OOMURO, Kazuya KIKUCHI, Xueting WANG, Takumi ITO, Kozo KINOSHITA, Toshiki SHIBANO
  • Patent number: 7049675
    Abstract: A high withstand voltage semiconductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: May 23, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kozo Kinoshita, Tetsuo Hatakeyama, Takashi Shinohe
  • Patent number: 6888195
    Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: May 3, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura, Kozo Kinoshita
  • Patent number: 6831345
    Abstract: A high withstand voltage semicnductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: December 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kozo Kinoshita, Tetsuo Hatakeyama, Takashi Shinohe
  • Publication number: 20040173820
    Abstract: A high withstand voltage semiconductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.
    Type: Application
    Filed: March 9, 2004
    Publication date: September 9, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kozo Kinoshita, Tetsuo Hatakeyama, Takashi Shinohe
  • Publication number: 20040056306
    Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
    Type: Application
    Filed: January 15, 2003
    Publication date: March 25, 2004
    Inventors: Wataru Saito, Ichiro Omura, Kozo Kinoshita
  • Publication number: 20030067033
    Abstract: A high withstand voltage semiconductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.
    Type: Application
    Filed: July 17, 2002
    Publication date: April 10, 2003
    Applicant: KABUSHHIKI KAISH TOSHIBA
    Inventors: Kozo Kinoshita, Tetsuo Hatakeyama, Takashi Shinohe
  • Patent number: 6469346
    Abstract: A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is [Acm−1], the amount of charge of electrons is q[C], and the drift speed of carriers is &ugr;drift[cms−1], the dosage n2 of the second offset layer is given by n2≧ID/(q &ugr;drift) [cms−2].
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: October 22, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Akio Nakagawa, Kozo Kinoshita
  • Patent number: 6259136
    Abstract: A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is [Acm−1], the amount of charge of electrons is q[C], and the drift speed of carriers is &ugr;drift[cms−1], the dosage n2 of the second offset layer is given by n2≧ ID/(q&ugr;drift)[cms−2].
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: July 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Akio Nakagawa, Kozo Kinoshita
  • Patent number: 5932897
    Abstract: A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is ?Acm.sup.-1 !, the amount of charge of electrons is q?C!, and the drift speed of carriers is .upsilon..sub.drift ?cms.sup.-1 !, the dosage n.sub.2 of the second offset layer is given by n.sub.2 .gtoreq.I.sub.D /(q.upsilon..sub.drift)?cms.sup.-2 !.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Akio Nakagawa, Kozo Kinoshita
  • Patent number: RE46799
    Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wataru Saito, Ichiro Omura, Kozo Kinoshita