Patents by Inventor Kranti V. Anand

Kranti V. Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5150019
    Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein a layer of a dielectric medium is disposed between the metal layers. A third metal layer is disposed above the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is disposed above the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: September 22, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Michael E. Thomas, Kranti V. Anand, deceased
  • Patent number: 5111355
    Abstract: A thin film capacitor for use in an integrated circuit includes a lower plate disposed on the silicon substrate of the integrated circuit. The lower plate comprises a barrier layer of conductive material which prevents transport of silicon from the silicon substrate into a layer of dielectric material which is disposed between the lower plate and an upper plate. A portion of the barrier layer can be consumed and transferred into dielectric material by, for example, high temperature oxidation which generates a symmetric series capacitor with the dielectric layer. A layer comprising an oxide of the barrier layer material is formed between the barrier layer and the dielectric layer by consuming an upper portion of the barrier layer.
    Type: Grant
    Filed: September 13, 1990
    Date of Patent: May 5, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Kranti V. Anand, Michael E. Thomas
  • Patent number: 5089433
    Abstract: A floating gate electrically erasable MOS transistor comprising a silicon substrate having source and drain regions and a channel region disposed between the source region and the drain region. The source and drain regions are formed from a semiconductor material having one conductivity type, and the channel region is formed from a semiconductor material having a conductivity type opposite the conductivity type of the semiconductor material forming the source and drain regions. A control gate region is formed in the silicon substrate horizontally spaced apart from the channel region. The gate region is formed from a semiconductor material having the same conductivity type as the semiconductor material forming the source and drain regions. A polysilicon layer bridges the control gate region and the channel region for communicating an electrical potential from the first gate region to the channel region.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: February 18, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Kranti V. Anand, Madhu Anand
  • Patent number: 4762728
    Abstract: A silicon nitride layer is prepared on the surface of a silicon substrate by carrying out a surface reaction on the substrate in a vacuum chamber that contains an electrode which is capacitively coupled to an rf generator. A second electrode within the chamber, or a metal wall of the chamber itself, is connected to ground. The silicon substrates to be treated are placed on one of the electrodes to be in electrical and physical contact therewith, and a reagent gas that contains nitrogen is introduced into the chamber. An rf voltage is then applied between the electrodes to ionize and activate the gas, and cause ions and other active species thereof to be directed into the silicon substrate. The nitrogen ions and other active species that are created as a result of the application of the rf power can be directed at the surface of a number of wafers simultaneously.
    Type: Grant
    Filed: November 26, 1985
    Date of Patent: August 9, 1988
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas Keyser, Bruce R. Cairns, Kranti V. Anand, William G. Petro, Michael L. Barry
  • Patent number: 4317686
    Abstract: A method of making a field-effect transistor is described in which first and second insulating layers are formed in crystalline material by ion implantation and, if necessary, annealing, further crystalline material being grown, if necessary, after the first layer has been implanted. Source and drain regions are defined in the material between the first and second layers, a layer of protective oxide is formed and metallization to form contacts for a gate region and the source and drain regions is deposited. Field-effect transistors made by the method are described and circuits containing such transistors can be separated by etching down to the first layer or by regions of amorphous material.
    Type: Grant
    Filed: June 27, 1980
    Date of Patent: March 2, 1982
    Assignee: National Research Development Corporation
    Inventors: Kranti V. Anand, John B. Butcher