Abstract: A large port count Fiber Channel switch. The large port count switch comprises multiple small switches. Inter-Switch links connect the small switches within the large port count switch. A set of routing rules governs the path data follows through the large port count switch.

Abstract: A large port count Fibre Channel switch. The large port count switch comprises multiple small switches. Inter-Switch links connect the small switches within the large port count switch. A set of routing rules governs the path data follows through the large port count switch.

Abstract: Virtual channels are used to improve quality of service through a large port count switch. Data frames are sent from one small switch to another small switch within the large port count switch on virtual channels. The use of virtual channels helps prevent congestion caused by a first external source device sending data to a first external destination device from affecting a second external source device sending data to a second external destination device.

Abstract: In a communication network system having a multi-switch Fiber Channel fabric, adjacent switches are communicatively coupled together by a plurality of links. The links are selectively determined to join a trunked group for enabling frames received at one switch to be routed over the links in the trunked group to the adjacent switch in an evenly distributed manner. In one embodiment, a link within the trunked group is coupled to a pair of ports residing on adjacent switches each having a designated trunking master port. The traffic load at one switch is routed through the trunking master port which distributes the load across multiple links and guarantees that the load is received at the adjacent switch with “in-order” delivery.

Abstract: A device that synchronizes circuits over asynchronous links is disclosed. Some embodiments of the invention include a device that comprises a plurality of circuits. One of the plurality of circuits is designated as a “master” circuit. The master circuit is configured to send a first synchronization signal to one or more of the plurality of circuits, and each circuit that receives the first synchronization signal is configured to responsively send a second synchronization signal to one or more of the plurality of circuits.

Abstract: A switch comprising front-end and back-end application specific integrated circuits (ASICs) is disclosed. Frame storage and retrieval in the switch is achieved by dividing a frame into equal sized portions that are sequentially stored in switch memory during an assigned time slot. Control logic coupled to the front-end and back-end ASICs assigns the time slot either dynamically or statically.

Abstract: A method that utilizes virtual channels and a common pool of credits, controlled by a transmitter to maximize the throughput across an Inter-Switch Link in a Fibre Channel network. Each virtual channel is allocated a minimum number of credits and the remaining credits of the ISL are held in a common pool. When needs arise, the credits in the pool will be allocated or reallocated to make the best use dynamically by the transmitter.

Abstract: A system and method for retrieving multi-speed data streams is described. The data streams are stored within a central memory containing a plurality of memory modules. A first embodiment provides for creating multiple timeslots and segments for accessing a memory module within the central memory. A second embodiment provides for buffering data streams to equalize the rate at which all the data streams are stored and retrieved from the central memory. An implementation of the second embodiment is described where unused timeslots are allocated for sending data from a memory module to a transmitting port.

Abstract: The link round trip delay between two switches in a Fibre Channel network may be determined by sending a particular timing signal value from an originating switch to a responding switch. The responding switch may store the timing signal value in an “echo” register for comparison to subsequently received timing signals. The originating switch may then send the pre-selected timing signal to the responding switch while simultaneously starting a timer. When the responding switch receives the timing signal, it may compare the value of the received signal to that stored in its echo register. If the value, is the same, the responding switch may retransmit—i.e., echo—the timing signal to the originating switch. When the originating switch receives the echoed timing signal, it may stop its timer and compute the link round trip delay time. The computed link round trip delay time between the originating switch and the responding switch may be advantageously used in fabric routing algorithms.

Abstract: A switch having a higher speed port, one or more slower speed ports, a larger buffer memory and numerous larger counters to achieve higher speed and longer range of communication. In one embodiment a larger switch having a larger buffer memory and larger counters connects to a smaller switch having a smaller buffer memory and smaller counters, the larger switch practically expanding the buffer memory and counters in the smaller switch. A combination of several counters can also avoid buffer overrun in any switches in the frame flow path due to the mismatch between the counter capabilities, the limitations of physical buffer spaces or the mismatch between transmission speeds. In another embodiment, the buffer spaces in several switches can be aggregated or cascaded along a frame path so that there are enough credits to maintain a high-speed transmission over a long distance.

Abstract: Virtual channels are used to improve quality of service through a large port count switch. Data frames are sent from one small switch to another small switch within the large port count switch on virtual channels. The use of virtual channels helps prevent congestion caused by a first external source device sending data to a first external destination device from affecting a second external source device sending data to a second external destination device.

Abstract: Virtual channels are used to improve quality of service through a large port count switch. Data frames are sent from one small switch to another small switch within the large port count switch on virtual channels. The use of virtual channels helps prevent congestion caused by a first external source device sending data to a first external destination device from affecting a second external source device sending data to a second external destination device.

Abstract: A link level flow control technique implements a “pull frame” transmission model in a Fibre Channel network. In one embodiment, frames remain in a first Fibre Channel device until they are requested by a second Fibre Channel device, wherein the second Fibre Channel device does not issue a request unless conditions are such that it can immediately transmit the frame toward its target destination. In another embodiment, a Fibre Channel device provides hardware messaging capability to support the pull model. In yet another embodiment, multiple Fibre Channel devices in accordance with the invention may be coupled to provide high port-count Fibre Channel switches.

Abstract: A device that synchronizes circuits over asynchronous links is disclosed. Some embodiments of the invention include a device that comprises a plurality of circuits. One of the plurality of circuits is designated as a “master” circuit. The master circuit is configured to send a first synchronization signal to one or more of the plurality of circuits, and each circuit that receives the first synchronization signal is configured to responsively send a second synchronization signal to one or more of the plurality of circuits.

Abstract: A switch comprising front-end and back-end application specific integrated circuits (ASICs) is disclosed. Frame storage and retrieval in the switch is achieved by dividing a frame into equal sized portions that are sequentially stored in switch memory during an assigned time slot. Control logic coupled to the front-end and back-end ASICs assigns the time slot either dynamically or statically.

Abstract: A method for providing flexibility in configuring Fibre Channel devices for different mode of operation. The method uses Path Numbering mechanism to identify a flow path with a Fibre Channel device. The Path Number is used to associate source port and destination port to make the intermediate connection transparent for those two ports. Devices, switches, systems and networks implementing this method are also disclosed.

Abstract: A device for converting between the trunked and untrunked transmission of Fibre Channel frame data is described. During conversion, the device manages the flow of frame data in both the egress (from Fibre Channel ports to a non-Fibre Channel port) and ingress (from a non-Fibre Channel port to Fibre Channel ports) directions. In the egress direction, the device operates as a FIFO to transmit all frames received from the Fibre Channel ports to the non-Fibre Channel ports. In the ingress direction, every frame received by the non-Fibre Channel port is stored in one of up to four storage segments based on the frame data's virtual circuit and path number identifiers. Frames are transmitted out of each storage segment in the order in which they are received therein. The device may be a stand-alone device. The device may also be incorporated into a Fibre Channel switch or other apparatus that connects to a Fibre Channel network or switch.

Abstract: A device for converting between the trunked and untrunked transmission of Fibre Channel frame data and for providing connections using longer distance links is described. During conversion, the device manages the flow of frame data in both the egress (from Fibre Channel ports to a non-Fibre Channel port) and ingress (from a non-Fibre Channel port to Fibre Channel ports) directions. In the egress direction, the device operates as a FIFO to transmit all frames received from the Fibre Channel ports to the non-Fibre Channel ports. In the ingress direction, every frame received by the non-Fibre Channel port is stored in one of up to four storage segments based on the frame data's virtual circuit and path number identifiers. Frames are transmitted out of each storage segment in the order in which they are received therein. The device may be a stand-alone device. The device may also be incorporated into a Fibre Channel switch or other apparatus that connects to a Fibre Channel network or switch.

Abstract: A switch having a higher speed port, one or more slower speed ports, a larger buffer memory and numerous larger counters to achieve higher speed and longer range of communication. In one embodiment a larger switch having a larger buffer memory and larger counters connects to a smaller switch having a smaller buffer memory and smaller counters, the larger switch practically expanding the buffer memory and counters in the smaller switch. A combination of several counters can also avoid buffer overrun in any switches in the frame flow path due to the mismatch between the counter capabilities, the limitations of physical buffer spaces or the mismatch between transmission speeds. In another embodiment, the buffer spaces in several switches can be aggregated or cascaded along a frame path so that there are enough credits to maintain a high-speed transmission over a long distance.

Abstract: A switch having a higher speed port, one or more slower speed ports, a larger buffer memory and numerous larger counters to achieve higher speed and longer range of communication. In one embodiment a larger switch having a larger buffer memory and larger counters connects to a smaller switch having a smaller buffer memory and smaller counters, the larger switch practically expanding the buffer memory and counters in the smaller switch. A combination of several counters can also avoid buffer overrun in any switches in the frame flow path due to the mismatch between the counter capabilities, the limitations of physical buffer spaces or the mismatch between transmission speeds. In another embodiment, the buffer spaces in several switches can be aggregated or cascaded along a frame path so that there are enough credits to maintain a high-speed transmission over a long distance.