Patents by Inventor Kris Baert

Kris Baert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120298172
    Abstract: A method for fabricating a photovoltaic module is disclosed. In one aspect, the method includes: providing a plurality of photovoltaic substrates having a front side; attaching the plurality of photovoltaic substrates to a transparent carrier with the front side of the photovoltaic substrates facing the carrier; and rear side processing of the plurality of photovoltaic substrates for forming photovoltaic cells, wherein rear side processing includes a single metallization process for forming electrical contacts to n-type regions and to p-type regions at the rear side of the plurality of photovoltaic cells and for interconnecting the photovoltaic cells within the photovoltaic module.
    Type: Application
    Filed: May 29, 2012
    Publication date: November 29, 2012
    Applicant: IMEC
    Inventor: Kris Baert
  • Patent number: 7723606
    Abstract: A thermoelectric generator (TEG) and a method of fabricating the TEG are described. The TEG is designed so that parasitic thermal resistance of air and height of legs of thermocouples forming a thermopile can be varied and optimized independently. The TEG includes a micromachined thermopile sandwiched in between a hot and a cold plate and at least one spacer in between the thermopile and the hot and/or cold plate. The TEG fabrication includes fabricating the thermopiles, a rim, and the cold plate.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: May 25, 2010
    Assignee: IMEC
    Inventors: Paolo Fiorini, Vladimir Leonov, Sherif Sedky, Chris Van Hoof, Kris Baert
  • Publication number: 20070040281
    Abstract: To provide a semiconductor device configured that a micro device having a device substrate, a function element provided on the device substrate and having an oscillator or a movable part, first lands provided on a surface of the device substrate by being arranged on its outer circumference portion of the function element, and bumps provided to the first lands is mounted on the circuit board having second lands formed to correspond to the bumps, from the bump formation surface side, so that the bumps and the second lands are electrically connected; on which a sealing resin layer is formed to go round the outer circumference portion of the function element to fix connection portions of the bumps and the second lands, and to seal a clearance between the device substrate and the circuit board; and a cavity portion is formed between the function element and the circuit board.
    Type: Application
    Filed: August 18, 2006
    Publication date: February 22, 2007
    Inventors: Hirokazu Nakayama, Akihiko Okubora, Yoichi Oya, Hirohito Miyazaki, Kris Baert, Ingrid De Wolf, Piet De Moor, Eric Beyne
  • Patent number: 7176111
    Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1?x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: February 13, 2007
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Kris Baert, Matty Caymax, Cristina Rusu, Sherif Sedky, Ann Witvrouw
  • Patent number: 6758958
    Abstract: The invention presents methods and systems for plating conductive patterns which at least result in a high uniformity and avoid parasitical plating effects. A plating system is disclosed for plating conductive patterns formed at a first surface of a substrate. The system is such that exposure surfaces not to be plated is inhibited. A first electrode of the system is immersed in the plating solution while the second electrode is in contact with another than the first surface of the substrate. The conductive patterns to be plated are temporarily electrically connected with the second electrode.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: July 6, 2004
    Assignees: Interuniversitair Micro-Elektronica Centrum, Siemens Aktiengesellschaft
    Inventors: Filip Van Steenkiste, Kris Baert, Walter Gumbrecht, Philippe Arquint
  • Publication number: 20030124761
    Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1−x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.
    Type: Application
    Filed: October 3, 2002
    Publication date: July 3, 2003
    Inventors: Kris Baert, Matty Caymax, Cristina Rusu, Sherif Sedky, Ann Witvrouw
  • Patent number: 6521109
    Abstract: A device for detecting an analyte in a sample comprising an active layer comprising at least a dielectric material, a source electrode, a drain electrode and a semiconducting substrate which acts as current pathway between source and drain. The conductivity of said semiconducting layer can be influenced by the interaction of the active layer with the sample containing the analyte to detect. The device is fabricated such that properties like low price, disposability, reduced drift of the device and suitability for biomedical and pharmaceutical applications are obtained. To fulfill these requirements, the device described in this application will be based on organic-containing materials.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: February 18, 2003
    Assignee: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventors: Carmen Bartic, Jef Poortmans, Kris Baert
  • Patent number: 6440662
    Abstract: A sensor for identifying molecular structures within a sample solution is disclosed. The sensor comprises an insulating layer with a plurality of interspaced channels therein having essentially the same direction. The channels furthermore have submicron dimensions. A method of fabricating a sensor for identifying molecular structures within a sample solution is also disclosed.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: August 27, 2002
    Assignee: Innogenetics N.V.
    Inventors: Peter Van Gerwen, Kris Baert, Rudi Rossau
  • Patent number: 6093577
    Abstract: A method of bonding a first substrate (10) to a second substrate (30) is described, comprising the steps of: coating an adhesive (28) onto a first major surface of said first substrate (10); aligning said first and second substrates (10, 30) so that said coated first major surface of said first substrate (10) is facing said second substrate (30) and is separated therefrom by a gap (47); deflecting at least one of said first and second substrates (10, 30) by exerting a pressure between said first and second substrates (10, 30) substantially at the center thereof so that the adhesive coating (28) substantially at the center of said first substrate (10) comes into contact with said second substrate (30); and allowing the remaining parts of said adhesive coated first major surface of said first substrate (10) to come into contact with said second substrate (30). Use of the method to produce composites, in particular transmissive liquid crystal display panels is also described.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: July 25, 2000
    Assignee: IMEC vzw
    Inventors: Sonja van der Groen, Kris Baert