Abstract: A radiation detector unit includes an interposer, at least one radiation sensor bonded to a front side of an interposer, an application-specific integrated chip (ASIC) bonded to a backside of the interposer, a carrier board bonded to the backside of the interposer and located on a backside of the ASIC, and at least one flex cable assembly attached to a respective side of the carrier board.

Abstract: A detector element circuit for a CT imaging system may include a plurality of sensors for detecting photons passing through an object and a first electronic component configured to determine an energy of photons detected by the plurality of sensors and generate photon count data, which may be a count of detected photons in one or more energy bins. The detector element circuit may further include a second electronic component configured to receive the photon count data from the first electronic component and is clocked at a first clock rate; a local memory storage configured to receive the photon count data from the second electronic component at the first clock rate and to output the photon count data at a second clock rate.

Abstract: Various embodiments described herein may include a detector array for a CT imaging system. The detector array includes a pixel array in which each pair of adjacent pixels in the pixel array may be separated by a collimator (e.g., located between each row and column of the pixel array) that absorbs photons and each pixel in the pixel array includes a sub-pixel array. The collimator absorbs photons that strike at a boundary between adjacent pixels. Each sub-pixel may have an anode that is connected to an ASIC channel. When a sub-pixel in a pixel detects a photon, signals of a plurality of sub-pixels in the pixel are automatically summed, including the sub-pixel that detected the photon.

Abstract: Various embodiments described herein may include a detector array for a CT imaging system. The detector array includes a pixel array in which each pair of adjacent pixels in the pixel array may be separated by a collimator (e.g., located between each row and column of the pixel array) that absorbs photons and each pixel in the pixel array includes a sub-pixel array. The collimator absorbs photons that strike at a boundary between adjacent pixels. Each sub-pixel may have an anode that is connected to an ASIC channel When a sub-pixel in a pixel detects a photon, signals of a plurality of sub-pixels in the pixel are automatically summed, including the sub-pixel that detected the photon.

Abstract: A detector slice circuit for a CT imaging system may include a plurality of sensors for detecting photons passing through an object and a first electronic component configured to determine an energy of photons detected by the plurality of sensors and generate photon count data, which may be a count of detected photons in one or more energy bins. The detector slice circuit may further include a second electronic component configured to receive the photon count data from the first electronic component and is clocked at a first clock rate; a local memory storage configured to receive the photon count data from the second electronic component at the first clock rate and to output the photon count data at a second clock rate.

Abstract: A bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive whatever logic value is applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1.

Abstract: An electrostatic discharge protection circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first switch apparatus comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain and substrate of the second NMOS FET connected to Vss, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.

Abstract: A resistor having a diffused impurity region in a semiconductor substrate, an insulated gate surrounding and defining the resistor, and a pair of separated conductive contacts to the diffused region within the boundary of the insulated gate for applying and receiving current passing through the resistor.

Abstract: A ring oscillator comprising: a plurality of sub-feedback loops, each comprising a pair of serially connected inverters and a feedback inverter having its input coupled to the output of the pair of inverters and its output connected to the input of the pair of inverters, the pairs of inverters being connected in a ring, and a downstream inverter of each respective pair of inverters forming an upstream inverter of an immediately following pair of inverters.

Abstract: An integrated circuit fuse with a fuse element having an "open" state and a "closed" state. A fuse status indicator is provided to indicate whether the fuse element is "open" or "closed". A current driver is electrically connected between the fuse element and electrical ground. One input of a dual input multiplexer is electrically connected to the fuse status indicator. The multiplexer's other input receives a fuse status simulation signal. A simulation mode switching signal is applied to the multiplexer's select input. A fuse output signal is consequently provided at the multiplexer's output to simulate operation of the fuse element in either the "open" or the "closed" state. The fuse element can be opened by causing a current having a value exceeding a preselected minimum value to flow through the fuse element for a preselected minimum time.

Abstract: An electrostatic discharge circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first CMOS inverter comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the source of the second NMOS FET connected to Vss, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.

Abstract: An integrated circuit output driver which reduces the effect of power supply and/or integrated circuit fabrication process variations on signal propagation delay. The output driver produces an output signal V.sub.out as an increased drive strength replica of an input signal V.sub.in. A pre-driver receives V.sub.in and produces an intermediate, inverted replica V.sub.int thereof. A driver is electrically connected to the pre-driver's output to receive V.sub.int. V.sub.out appears at the driver's output as an inverted, strengthened replica of V.sub.int. A first feedback circuit electrically connected between the driver's input and output applies a pull-down signal to the driver's input in response to a falling edge of V.sub.in, with the pull-down signal's strength varying in inverse proportion to propagation delay of the falling edge of V.sub.in.

Abstract: An electrostatic discharge (ESD) protection structure for protection of a circuit to which an operation voltage is to be applied, comprising a silicon controlled rectifier (SCR) connected between ground and a pad of the circuit to be protected, the SCR including a resistor apparatus connected to the pad for controlling the breakdown voltage of the SCR, and apparatus for controlling the resistor apparatus to a high resistance value in the absence of the application of the operation voltage whereby the SCR is controlled to break down at a low ESD voltage which is lower than a circuit damaging voltage, and to be of low resistance value upon the application of the operation voltage whereby the SCR is controlled to break down at an ESD voltage which is higher than the low ESD voltage.