Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

Abstract: Methods of forming integrated circuitry memory devices are described. In a preferred implementation, methods of forming DRAM arrays are described. According to one aspect of the invention, a plurality of continuous active areas are formed relative to a semiconductive substrate. A plurality of word lines and active area isolation lines are formed over the continuous active areas. An insulative layer is formed over the word lines and active area isolation lines and in a common masking step, both capacitor contact openings and bit line contact openings are patterned over the insulative layer. Subsequently, capacitor contact openings and bit line contact openings are etched through the insulative layer over the continuous active area. In a preferred implementation, the capacitor contact openings and the bit line contact openings are contemporaneously patterned and etched. Subsequently, conductive material is formed within the openings to provide conductive plugs.

Abstract: Methods of forming integrated circuitry memory devices are described. In a preferred implementation, methods of forming DRAM arrays are described. According to one aspect of the invention, a plurality of continuous active areas are formed relative to a semiconductive substrate. A plurality of word lines and active area isolation lines are formed over the continuous active areas. An insulative layer is formed over the word lines and active area isolation lines and in a common masking step, both capacitor contact openings and bit line contact openings are patterned over the insulative layer. Subsequently, capacitor contact openings and bit line contact openings are etched through the insulative layer over the continuous active area. In a preferred implementation, the capacitor contact openings and the bit line contact openings are contemporaneously patterned and etched. Subsequently, conductive material is formed within the openings to provide conductive plugs.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node, the capacitor plate comprising conductively doped polysilicon; c) providing a predominately amorphous electrically conductive layer over the first capacitor plate; d) providing a capacitor dielectric layer over the amorphous electrically conductive layer; and e) providing a second electrically conductive capacitor plate over the capacitor dielectric layer. A capacitor construction is also disclosed. The invention has greatest utility where the polysilicon layer covered with the amorphous conductive layer is a roughened outer layer, such as provided with hemispherical grain polysilicon. The preferred amorphous electrically conductive layer is metal organic chemical vapor deposited TiCXNyOZ, where “x”is in the range of from 0.01 to 0.5, and “y” is in the range of from 0.99 to 0.

Abstract: Methods of forming integrated circuitry memory devices are described. In a preferred implementation, methods of forming DRAM arrays are described. According to one aspect of the invention, a plurality of continuous active areas are formed relative to a semiconductive substrate. A plurality of word lines and active area isolation lines are formed over the continuous active areas. An insulative layer is formed over the word lines and active area isolation lines and in a common masking step, both capacitor contact openings and bit line contact openings are patterned over the insulative layer. Subsequently, capacitor contact openings and bit line contact openings are etched through the insulative layer over the continuous active area. In a preferred implementation, the capacitor contact openings and the bit line contact openings are contemporaneously patterned and etched. Subsequently, conductive material is formed within the openings to provide conductive plugs.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node, the capacitor plate comprising conductively doped polysilicon; c) providing a predominately amorphous electrically conductive layer over the first capacitor plate; d) providing a capacitor dielectric layer over the amorphous electrically conductive layer; and e) providing a second electrically conductive capacitor plate over the capacitor dielectric layer. A capacitor construction is also disclosed. The invention has greatest utility where the polysilicon layer covered with the amorphous conductive layer is a roughened outer layer, such as provided with hemispherical grain polysilicon. The preferred amorphous electrically conductive layer is metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.

Abstract: Methods of forming integrated circuitry memory devices are described. In a preferred implementation, methods of forming DRAM arrays are described. According to one aspect of the invention, a plurality of continuous active areas are formed relative to a semiconductive substrate. A plurality of word lines and active area isolation lines are formed over the continuous active areas. An insulative layer is formed over the word lines and active area isolation lines and in a common masking step, both capacitor contact openings and bit line contact openings are patterned over the insulative layer. Subsequently, capacitor contact openings and bit line contact openings are etched through the insulative layer over the continuous active area. In a preferred implementation, the capacitor contact openings and the bit line contact openings are contemporaneously patterned and etched. Subsequently, conductive material is formed within the openings to provide conductive plugs.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node, the capacitor plate comprising conductively doped polysilicon; c) providing a predominately amorphous electrically conductive layer over the first capacitor plate; d) providing a capacitor dielectric layer over the amorphous electrically conductive layer; and e) providing a second electrically conductive capacitor plate over the capacitor dielectric layer. A capacitor construction is also disclosed. The invention has greatest utility where the polysilicon layer covered with the amorphous conductive layer is a roughened outer layer, such as provided with hemispherical grain polysilicon. The preferred amorphous electrically conductive layer is metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node, the capacitor plate comprising conductively doped polysilicon; c) providing a predominately amorphous electrically conductive layer over the first capacitor plate; d) providing a capacitor dielectric layer over the amorphous electrically conductive layer; and e) providing a second electrically conductive capacitor plate over the capacitor dielectric layer. A capacitor construction is also disclosed. The invention has greatest utility where the polysilicon layer covered with the amorphous conductive layer is a roughened outer layer, such as provided with hemispherical grain polysilicon. The preferred amorphous electrically conductive layer is metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node, the capacitor plate comprising conductively doped polysilicon; c) providing a predominately amorphous electrically conductive layer over the first capacitor plate; d) providing a capacitor dielectric layer over the amorphous electrically conductive layer; and e) providing a second electrically conductive capacitor plate over the capacitor dielectric layer. A capacitor construction is also disclosed. The invention has greatest utility where the polysilicon layer covered with the amorphous conductive layer is a roughened outer layer, such as provided with hemispherical grain polysilicon. The preferred amorphous electrically conductive layer is metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: An embodiment of the present invention depicts a storage capacitor comprising: a bottom plate structure having a hemispherical grain silicon surface; a titanium nitride layer adjacent and coextensive the hemispherical grain silicon; an insulating layer adjacent and coextensive the titanium nitride layer; and a top plate structure comprising conductively doped polysilicon layer superjacent and coextensive the insulating layer.

Abstract: An embodiment of the present invention depicts a storage capacitor comprising: a bottom plate structure having a hemispherical grain silicon surface; a titanium nitride layer adjacent and coextensive the hemispherical grain silicon; an insulating layer adjacent and coextensive the titanium nitride layer; and a top plate structure comprising conductively doped polysilicon layer superjacent and coextensive the insulating layer.