Abstract: An exoskeleton system that comprises: one or more actuator units, the one or more actuator units including an actuator; one or more sensors; and an exoskeleton device that includes: an actuation system, and a processor and memory, the memory storing instructions, that when executed by the processor, are configured to control the exoskeleton system to: cause actuation of the actuator of the one or more actuator units.

Abstract: An exoskeleton system, the exoskeleton system comprising one or more actuator units that include a fluidic actuator, one or more sensors and an exoskeleton device. The exoskeleton device includes a fluidic system, and a processor and memory, the memory storing instructions, that when executed by the processor, are configured to control the exoskeleton system to introduce fluid to the fluidic actuator of the one or more actuator units to cause actuation of the fluidic actuator of the one or more actuator units. The exoskeleton system may be configured to operate in, on or around a body of water and can be water and/or corrosion resistant.

Abstract: An exoskeleton system that includes at least one actuator unit having an upper arm and a lower arm that are rotatably coupled via a joint and a fluidic actuator that extends between the upper arm and the lower arm.

Abstract: An exoskeleton system, the exoskeleton system comprising one or more actuator units that include a fluidic actuator, one or more sensors and an exoskeleton device. The exoskeleton device includes a fluidic system, and a processor and memory, the memory storing instructions, that when executed by the processor, are configured to control the exoskeleton system to introduce fluid to the fluidic actuator of the one or more actuator units to cause actuation of the fluidic actuator of the one or more actuator units. The exoskeleton system may be configured to operate in, on or around a body of water and can be water and/or corrosion resistant.

Abstract: An exoskeleton system comprising at least one leg actuator unit configured to be coupled to leg of a user, the leg actuator unit including: an upper arm and a lower arm that are rotatably coupled via a joint, the joint positioned at a knee of the user with the upper arm coupled about an upper leg portion of the user above the knee and with the lower arm coupled about a lower leg portion of the user below the knee, a leg-actuator-unit user interface comprising a plurality of input and feedback elements, and an actuator that extends between the upper arm and lower arms.

Abstract: A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.

Abstract: A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.

Abstract: A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further configured to couple an equalization potential to the first and second power supply nodes when the latch is operating in an equalization mode.