Abstract: A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common device layer within a single-crystal semiconductor layer of an SOI substrate. A gate of the first FET overlies an upper surface of the common device layer, and a gate of the second FET underlies a lower surface of the common device layer remote from the upper surface. The first and second FETs share a common diffusion region disposed in the common device layer and are conductively interconnected by the common diffusion region. The common diffusion region is operable as at least one of a source region or a drain region of the first FET and is simultaneously operable as at least one of a source region or a drain region of the second FET.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A process and apparatus for generating a mail message for multiple recipients which identify to a respective recipient an attention level. A list of addresses for the recipient is created along with a mail message to be sent to all of the recipients. Appended to each address is a tag representing an attention level for the recipients. A text message is created for each of the recipients which includes the addresses and related tag. The text message and related tags are forwarded to the recipients. Each recipient displays on an electronic mail terminal a text message addressed to him. The attention level indication contained in the tag of the message is used to alert the recipient with an attention level assigned to the message for the recipient. The attention level may also be indicated by highlighting specific portions of the text in associating a tag with the recipient's address identifying for that recipient a portion of the text message to be highlighted.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A method of forming multiple SOI wafers from a plurality of individual wafers each having a first side and a second side. The method includes forming an oxide surface on the first side on each of the plurality of individual wafers and forming a hydrogen rich region at a preselected depth on the second side on each of the plurality of individual wafers. The wafers are then bonded into a stacked configuration and heat treated to fracture the wafers at the hydrogen rich regions. This fracture forms at least two SOI wafers.

Abstract: A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut.RTM. process. Because of the use of the variation on the Smart-Cut.RTM. process, diffusion regions are removed without significantly affecting the specifications of the semiconductor wafer. Therefore, a defective or rejected wafer can be restored to near original condition for use in semiconductor manufacturing.

Abstract: A process applicable to the production of monocrystalline films improves on the Smart-Cut.RTM. process by using an etch stop layer in conjunction with the Smart-Cut.RTM. process. Because of the etch stop layer, no chemical-mechanical polishing (CMP) is required after fabrication. Thus, the thickness and smoothness of the device layer in the fabricated silicon on insulator (SOI) substrate is determined by the uniformity and smoothness of the deposited layers and wet etch selectivity, as opposed to the CMP parameters. Therefore, the smoothness and uniformity of the device layer are improved.

Abstract: A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum allow form a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the-germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.

Abstract: An electrically blowable fuse structure usable with organic insulators in microelectronic parts is provided. The fuse structure is made of a first heat resistant member, a fusing element and a second heat resistant member. The heat resistant members are in substantial contact with the fuse and thermally insulate the fuse from the organic insulator. The ends of each fuse are electrically connected to a pair conductors.A process for fabricating an electrically blowable fuse structure usable with an organic insulator is provided. A substrate with an organic insulator coating and containing electrically conductive features with exposed contacts is provided. A heat shield layer and a fuse layer are deposited sequentially and patterned by subtractive etching. Plurality of conductors are formed over so as to electrically connect each fuse element to a pair of conductors. A second heat resistant member is formed over the fuse area and the substrate is subsequently quoted with an organic insulator.

Abstract: The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.

Abstract: An electrically blowable fuse structure usable with organic insulators in microelectronic parts is provided. The fuse structure is made of a first heat resistant member, a fusing element and a second heat resistant member. The heat resistant members are in substantial contact with the fuse and thermally insulate the fuse from the organic insulator. The ends of each fuse are electrically connected to a pair conductors.

Abstract: An aerosol cleaning apparatus for cleaning a substrate includes an aerosol producing means having a nozzle head. The nozzle head is positioned at a selected proximity and orientation to the substrate which is held by a rotatable holder. The aerosol spray dislodges particles from the substrate and the rotation of the substrate further assists in the removal of the loosened particles. A method of aerosol cleaning includes rotating a substrate at a preselected speed and spraying an aerosol jet in conjunction with the rotation to help in the removal of particles from the substrate.

Abstract: An integrated circuit having organic dielectric between interconnection layers eliminates damage caused by vapors outgassing from the organic dielectric by the use of a two-component organic layer having a breathable etch resistant organic layer above the main organic dielectric layer, both of the organic layers remaining in the final circuit. The etch resistant layer is resistant to the etchant used to pattern the layer of interconnect above the organic dielectric.

Abstract: A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum alloy form forming a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.

Abstract: An integrated circuit chip including a first and a higher second surface levels with an abrupt sidewall step transition therebetween, and having a first layer of a first conductive material disposed over the first surface level and over the second surface level, but terminating on the first surface level in a first end portion which extends up to but does not touch the sidewall. This end portion comprises a conductive material which has been converted to an insulator. A second layer of a second conductive material is disposed on top of the first conductive layer with essentially no conductive material conversion to insulator therein adjacent to the abrupt sidewall transition. In a preferred embodiment, the conductive material is an alloy of aluminum and the end portion is aluminum oxide.

Abstract: Electromigration activity is decreased and lifetime is extended in solder stripes employed as conductors and terminals on microelectronic devices by forming an alloy of a solute element, such as copper, with tin in a lead/tin solder and providing a substantially uniform distribution of particles of the intermetallic compound in the solder. The concentration of the solute element is maintained at less than about three times the tin concentration and less than about 10% of the amount of the solder.

Abstract: A method of coating or cladding existing metallurgical features of a dielectric substrate by sequentially blanket coating the substrate with two discrete levels of diverse metals having differential in melting point and forming a continuous series of alloy solid solutions whose solidus curve lies intermediate the melting points of the two component metals, with the metal having the lower melting point disposed adjacent said substrate, followed by heating of the substrate to a temperature slightly above melting point of the lower melting metal but not exceeding the liquidus temperature of a completely homogenized alloy corresponding to amounts of the metals deposited, with cooling of the substrate to delaminate the metal coatings on the bare surface areas of said substrate, and mechanically removing said delaminated metal coatings to retain a bonded cladding comprised of said metals on said metallurgical features.

Abstract: A thin film capacitor having a dual bottom electrode is provided. The bottom electrode includes a first layer of metal and a second layer of platinum, the metal of the first layer having the characteristic of forming a stable intermetallic phase with platinum during heat treatment. The first layer metal may be selected from the group consisting of Hf, Zr and Ta. The thin film capacitor may be employed as a decoupling capacitor in VLSI devices.