Patents by Inventor Kris Venkatraman Srikrishnan

Kris Venkatraman Srikrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5897370
    Abstract: A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1 Torr. Step coverage of the fill material and sputtering parameters are chosen to satisfy a predetermined relationship. The upper surface of the substrate comprises regions of exposed aluminum, aluminum-copper or copper alloys. After filling the vias and lines, the exposed aluminum, aluminum-copper or copper alloys are reacted with a gas containing germanium to form a germanium alloy over the upper surface of the substrate.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: April 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Rajiv Vasant Joshi, Manu Jamnadas Tejwani, Kris Venkatraman Srikrishnan
  • Patent number: 5877084
    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6, can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: March 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: Rajiv Vasant Joshi, Manu Jamnadas Tejwani, Kris Venkatraman Srikrishnan
  • Patent number: 5856026
    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: January 5, 1999
    Assignee: International Business Machines Corporation
    Inventors: Rajiv Vasant Joshi, Manu Jamnadaf Tejwani, Kris Venkatraman Srikrishnan
  • Patent number: 5787098
    Abstract: A system and method for evaluating solder ball connections to a flip-chip or the like integrated circuit device through an extension of boundary scan testing circuits and techniques. The existence, size, and connective efficacy of solder balls deposited on pads are indirectly verified through the inclusion of a boundary scan driver and receiver with each pad. The respective drivers and receivers are connected to the complementing sections of a segmented pad metallurgy. The formation of a correct size solder ball connects the driver and receiver to allow boundary scan verification of all the electrical connections in the path. Thereby, low contact testing can be used to verify the integrity of the integrated circuit as well as any solder ball type die (chip) output contacts.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: July 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Sumit DasGupta, Kris Venkatraman Srikrishnan, Ronald Gene Walther
  • Patent number: 5731245
    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap and polish stop of W.sub.x Ge.sub.y, a tungsten-germanium alloy. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: March 24, 1998
    Assignee: International Business Machines Corp.
    Inventors: Rajiv Vasant Joshi, Manu Jamnadas Tejwani, Kris Venkatraman Srikrishnan