Patents by Inventor Krishan Singh

Krishan Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260254548
    Abstract: Systems and methods are provided for selecting a clock source for synchronization recovery. According to one implementation, a method includes a step of receiving Master clock signals and source recovery indicators from upstream branches of a communications system, each source recovery indicator corresponding to a respective Master clock signal. Furthermore, the method includes a step of utilizing a prioritization strategy to prioritize the Master clock signals based on information derived from the source recovery indicators. During synchronization recovery, the method also includes a step of selecting one of the Master clock signals based on the prioritization strategy to act as a temporary synchronization source in a downstream branch of the communications system.
    Type: Application
    Filed: April 10, 2025
    Publication date: August 27, 2026
    Applicant: Ciena Corporation
    Inventors: Amit Kumar Choudhary, Krishan Singh, Sharad Kumar Srivastava, Hirdesh Srivastava
  • Patent number: 12634030
    Abstract: Aspects of the subject disclosure may include, for example, a device, including: a processing system including a processor; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: receiving an indication of a priority level of an interworking function used by a boundary clock node; and selecting a best master clock using an algorithm that considers the priority level of the boundary clock node. Other embodiments are disclosed.
    Type: Grant
    Filed: January 18, 2024
    Date of Patent: May 19, 2026
    Assignee: CIENA CORPORATION
    Inventors: Sharad Kumar Srivastava, Vineet Kumar Garg, Krishan Singh, Vikas Joshi
  • Publication number: 20250184023
    Abstract: Aspects of the subject disclosure may include, for example, a device, including: a processing system including a processor; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: receiving an indication of a priority level of an interworking function used by a boundary clock node; and selecting a best master clock using an algorithm that considers the priority level of the boundary clock node. Other embodiments are disclosed.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 5, 2025
    Applicant: CIENA CORPORATION
    Inventors: Sharad Kumar Srivastava, Vineet Kumar Garg, Krishan Singh, Vikas Joshi
  • Publication number: 20250184025
    Abstract: Aspects of the subject disclosure may include, for example, a device, including: a processing system including a processor; a clock; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: advertising via Border Gateway Protocol (BGP) a capability as a precision timing protocol (PTP) master clock through an Internet Protocol (IP)/Multi-Protocol Label Switching (MPLS) network, wherein the advertising includes an IP address of the device; receiving a unicast signaling mechanism from a PTP client node in the network; and sending clock messages to the PTP client node responsive to accepting the PTP client node. Other embodiments are disclosed.
    Type: Application
    Filed: January 30, 2025
    Publication date: June 5, 2025
    Applicant: CIENA CORPORATION
    Inventors: Sharad Kumar Srivastava, Vineet Kumar Garg, Krishan Singh, Vijendra Singh Chauhan
  • Publication number: 20250184024
    Abstract: Aspects of the subject disclosure may include, for example, a device that includes a processing system including a processor; a clock; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: advertising a capability as a precision timing protocol (PTP) master clock through an Internet Protocol (IP) network, wherein the advertising includes an IP address of the device; receiving a unicast signaling mechanism from a PTP client node in the network; and sending clock messages to the PTP client node responsive to accepting the PTP client node. Other embodiments are disclosed.
    Type: Application
    Filed: January 23, 2024
    Publication date: June 5, 2025
    Applicant: CIENA CORPORATION
    Inventors: Sharad Kumar Srivastava, Vineet Kumar Garg, Krishan Singh, Vijendra Singh Chauhan