Abstract: A processor includes a triple-base-number-system (TBNS) Arithmetic Unit architecture. TBNS processing enables extremely high-performance digital signal processing of larger word-size data, and enables a processor architecture having reduced hardware complexity and power dissipation. With demanding signal processing applications a TBNS processing is much more efficient as compared to either traditional SBNS or even DBNS. In a processor, a Multiplication Unit comprises at least three Adders to each add an extracted pair of like powers of two numbers to be multiplied. A result of one Adder controls a number of bits of shift of a barrel shifter, and a result of remaining Adders are input to a lookup table feeding the barrel shifter. A register holds an output of the barrel shifter. TBNS processing system includes a binary-to-TBNS data converter adapting a Binary-Search-Tree and Range Table to convert binary data/numbers into TBNS representation.